de2_tv.fit.summary

来自「本源码是用verilog编写控制LCD——使用Quartusii」· SUMMARY 代码 · 共 15 行

Fitter Status : Successful - Tue Jul 01 20:09:08 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : DE2_TV
Top-level Entity Name : DE2_LCD
Family : Cyclone II
Device : EP2C35F672C8
Timing Models : Final
Total logic elements : 105 / 33,216 ( < 1 % )
Total registers : 51
Total pins : 101 / 475 ( 21 % )
Total virtual pins : 0
Total memory bits : 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )