freqdiv.vhd

来自「系统功能 带有约会提醒功能的电子日历」· VHDL 代码 · 共 67 行

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    00:14:41 06/14/2007 
-- Design Name: 
-- Module Name:    freqdiv - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY freqdiv IS
	PORT(a	: IN STD_LOGIC;
	     b	: OUT STD_LOGIC);
END freqdiv;

ARCHITECTURE Behavioral OF freqdiv IS

SIGNAL count1	: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL count2	: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL count3	: STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN
		PROCESS(a)
		BEGIN
			IF(a'event AND a = '1') THEN
				IF(count1 = "11111111") THEN
					IF(count2 = "11111111") THEN
						IF(count3 = "11111111") THEN
							b <= '1';
							count3 <= (OTHERS => '0');
						ELSE
							b <= '0';
							count3 <= count3 + 1;
						END IF;
						count2 <= (OTHERS => '0');
					ELSE
						count2 <= count2 + 1;
					END IF;
				    count1<=(others=>'0');
				else  
				    count1 <= count1 + 1;
				END IF;
			END IF;
		END PROCESS;

END Behavioral;