disp_coder.vhd

系统功能 带有约会提醒功能的电子日历

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    00:06:07 06/14/2007 
-- Design Name: 
-- Module Name:    disp_coder - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY disp_coder IS
	PORT(a	: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	     b	: OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END disp_coder;

ARCHITECTURE Behavioral OF disp_coder IS

BEGIN
		PROCESS(a)--译码显示。
		BEGIN
			CASE a IS
					WHEN "0000" => b <= "1000000";--加NOT，以便于共阳共阴转换
					WHEN "0001" => b <= "1111001";--GFEDCBA,高位是G
					WHEN "0010" => b <= "0100100";--LED 7段译码电路。--共阳接法
					WHEN "0011" => b <= "0110000";
					WHEN "0100" => b <= "0011001";
					WHEN "0101" => b <= "0010010";
					WHEN "0110" => b <= "0000010";
					WHEN "0111" => b <= "1111000";
					WHEN "1000" => b <= "0000000";
					WHEN "1001" => b <= "0010000";
					WHEN OTHERS => b <= "1000000";
			END CASE;
		END PROCESS;

END Behavioral;