📄 cdbltcy.txt
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add.w temp1, integ_total
jnc break_1 ; jump if no overflow
inc.w div_count_1 ; count shift/div by 2 events
; end integration of samples
; begin peak count
break_1 cmp.w avg_temp_1, res_avg
jge break_2 ; jump if res_avg > avg_temp_1, signed
cmp.w avg_temp_1, avg_temp_2
jge break_2 ; jump if avg_temp_2 > avg_temp_1, signed
inc.w peaks
; end peak count
break_2 ; begin zero count
cmp.w #0, avg_temp_1
jl test_2 ; jump if avg_temp_1 < 0, signed
cmp.w #0, res_avg
jge break_3 ; jump if res_avg > 0, signed
jmp count
test_2 cmp.w #0, res_avg
jl break_3 ; jump if res_avg < 0, signed
count inc zeros
break_3 ; end zero count
mov.w avg_temp_1, avg_temp_2 ; save previous averaging results, avg_temp_2 holds result(n-2)
mov.w res_avg, avg_temp_1 ; save previous averaging results, avg_temp_1 holds result(n-1)
mov.w temp1, INPUT ; temp1 holds current sample
call #WDF
; begin integration of samples of WDF output
mov.w OUTP, temp1
test_1 cmp.w #0, temp1
jl break_4 ; jump if temp1 < 0
bic.w #C, SR
add.w temp1, integ_HPB
jnc break_4
inc.w div_count_2 ; count shift/div by 2 events
; end integration of samples of WDF output
break_4 ; begin ratio HP band/total band
cmp.w #2336, sample_count ; 2336 samples reached (60ms)?
jlo end_analyz ; if sample_count < 2336, unsigned
ADC_off bic.w #ENC+ADC10IE, &ADC10CTL0; disable ADC10
bic.w #OAPM0+OAPM1,&OA0CTL0_ ; OP0 amplifier off
bic.w #OAPM0+OAPM1,&OA1CTL0_ ; OP1 filter off
bic.b #BIT0, P4OUT ; mic off
bic.b #BIT4, P2OUT ; offset off
; begin pre-scaling
mov.w div_count_1, temp1
mov.w div_count_2, temp2
cmp.w temp2, temp1
jlo ratio_f_1 ; jump if div_count_1 < div_count_2
sub.w #0, temp1 ; begin shift values equal to their overflows
jz break_5 ; jump if div_count_1 = 0 -> if no overflow at integ_total occured
loop_1 cmp.w #1, temp2
jlo rrc_C_0 ; jump if div_count_2=0 and div_count_1!=0
bis.w #C, SR
rrc.w integ_HPB ; shifts integ_HPB through carry=1
dec.w temp2 ; decrement div_count_2 number once per shift operation
jmp cmp_temp1 ; finish div_count_2 test
rrc_C_0 bic.w #C, SR
rrc.w integ_HPB ; shifts integ_HPB through carry=0
cmp_temp1 bis.w #C, SR
rrc.w integ_total
dec.w temp1 ; sets carry while div_count_1!=0
cmp.w #1, temp1
jge loop_1 ; end shift values equal to their overflows
; end pre-scaling
break_5 ; begin division quotient=dividend/divisor
bit.w #8000, integ_HPB
jz cont_11 ; jump if integ_HPB(divisor) MSB="0"
bic.w #C, SR
rrc.w integ_HPB ; MSB="0" required
bic.w #C, SR
rrc.w integ_total ; shift to keep ratio konstant
cont_11 cmp.w #0,integ_HPB ; prevent division by zero
jeq ratio_f_1
mov.w integ_total, R15 ; R15 has dividend, R15 holds result
mov.w integ_HPB, R14 ; R14 has divisor
mov.w #16,R11 ; counter 16bit register = 16shifts
clr.w R13 ; A, R13 finaly holds the remainder
start rla.w R15 ; shift left by one
rlc.w R13 ; catches first bit of shiftet dividend
bis.w #1, R15 ; set last bit of dividend
sub.w R14,R13 ; A-divisor=A
jge loc1 ; A>=0 ?
add.w R14,R13
bic.w #1, R15 ; clear last bit depending on result of A-divisor=A
; A<0 bit one of dividend=1, A>0 bit one of dividend=0
loc1 dec.w R11
cmp.w #0,R11
jnz start
; end division quotient=dividend/divisor
; begin floating point of division
clr R12
rra R14 ; divider/4
rra R14
loop_2 sub.w R14, R13
cmp.w #0, R13
jl cont_test;
inc R12 ; counter, how often is divider/4 in remainder
cmp #3, R12 ; if more than 3 loops
jge cont_test
jmp loop_2
; end floating point of division
cont_test ; begin data interpretation
cmp.w #7, R15
jge ratio_f_1
cmp.w #1, R15
jl ratio_f_1
jne check_peaks
cmp #3, R12 ; check decimal point, 3=0.75
jl ratio_f_1
jmp check_peaks
check_peaks cmp.w #160, peaks
jlo peakfalse
cmp.w #320, peaks
jge peakfalse
check_zeros cmp.w #95, zeros
jlo zerofalse
cmp.w #300, zeros
jge zerofalse
jmp check
ratio_f_1 inc.w ratio_false ; set ratio false flag
jmp check_peaks
peakfalse inc.w peak_false ; set peak false flag
jmp check_zeros
zerofalse inc.w zero_false ; set zero crossing false flag
check cmp.w #1, ratio_false
jge break_6
cmp.w #1, peak_false
jge break_6
cmp.w #1, zero_false
jge break_6
; end data interpretation
glass_break bis.b #BIT0,&P1OUT ; set P1.0 = 1, turn led on
bis.b #BIT7,&P3OUT ; set P3.7 = 1, turn buzzer on
call #delay_12Mhz ; delay led/buzzer active time
bic.b #BIT0,&P1OUT ; set P1.0 = 0, turn led off
bic.b #BIT7,&P3OUT ; set P3.7 = 0, turn buzzer off
break_6 bit.w #BIT3, &OA1CTL0_
jz cont_7 ; jump if AAF off
call #SetupADC10_wakeup_AAF ; execute if AAF on
jmp cont_8
cont_7 call #SetupADC10_wakeup_no_AAF
call #INITMEM
cont_8 call #SetDCO_8Mhz
bis.w #MC_1, TACTL ; up mode, TA start
mov.b #LPM3+GIE, SR ; enable LPM3 mode and global interrupts
end_analyz ret
;-------------------------------------------------------------------------------
SetupADC10_wakeup_AAF; Setup ADC10 comparator
;-------------------------------------------------------------------------------
mov.w #ADC10SHT_1+ADC10SR, &ADC10CTL0
; 8 ADC10CLK S&H, max 50ksps
mov.w #INCH_13+ADC10DIV_2+ADC10SSEL_3+CONSEQ_0, &ADC10CTL1
; Channel A13, ADC10CLK=SMCLK/3
; Single Channel Conversion
ret
;-------------------------------------------------------------------------------
SetupADC10_wakeup_no_AAF; Setup ADC10 comparator
;-------------------------------------------------------------------------------
mov.w #ADC10SHT_1+ADC10SR, &ADC10CTL0
; 8 ADC10CLK S&H, max 50ksps
mov.w #INCH_1+ADC10DIV_2+ADC10SSEL_3+CONSEQ_0, &ADC10CTL1
; Channel A1, ADC10CLK=SMCLK/3
; Single Channel Conversion
ret
;-------------------------------------------------------------------------------
SetupADC10_cont_AAF; Setup ADC10 signal analysis
;-------------------------------------------------------------------------------
mov.w #ADC10SHT_3+ADC10SR+MSC+ADC10ON+ADC10IE, &ADC10CTL0
; Ref: VR+ = Vcc and VR- = Vss
; 64 ADC10CLK S&H, max 50ksps
; Multi S&C, ADC on, ADC IE
mov.w #INCH_13+ADC10DIV_3+ADC10SSEL_3+CONSEQ_2, &ADC10CTL1
; Channel A13, ADC10CLK=SMCLK/4
; Repeat Single Channel Conversion
ret
;-------------------------------------------------------------------------------
SetupADC10_cont_no_AAF; Setup ADC10 signal analysis
;-------------------------------------------------------------------------------
mov.w #ADC10SHT_3+ADC10SR+MSC+ADC10ON+ADC10IE, &ADC10CTL0
; Ref: VR+ = Vcc and VR- = Vss
; 64 ADC10CLK S&H, max 50ksps
; Multi S&C, ADC on, ADC IE
mov.w #INCH_1+ADC10DIV_3+ADC10SSEL_3+CONSEQ_2, &ADC10CTL1
; Channel A1, ADC10CLK=SMCLK/4
; Repeat Single Channel Conversion
ret
;-------------------------------------------------------------------------------
SetupOP1_2; Setup OP1 & OP2
;-------------------------------------------------------------------------------
OP0 mov.b #OAFBR_6+OAFC_6+OANEXT,&OA0CTL1_
; Inverting PGA, gain=-7
; inv input external available
mov.b #OAN_1+OAP_0+OAPM_0+OAADC1,&OA0CTL0_
; inv input OA0I1 P2.2
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