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module act_low1
q0,q1 pin istype 'reg';
clock pin;
reset pin;
equations
[q1,q0].clk = clock;
![q1,q0] := (![q1,q0] + 1) & !reset;
test_vectors ([clock,reset] -> [!q1,!q0])
[ .c. , 1 ] -> [ 0 , 0 ];
[ .c. , 0 ] -> [ 0 , 1 ];
[ .c. , 0 ] -> [ 1 , 0 ];
[ .c. , 0 ] -> [ 1 , 1 ];
[ .c. , 0 ] -> [ 0 , 0 ];
[ .c. , 0 ] -> [ 0 , 1 ];
[ .c. , 1 ] -> [ 0 , 0 ];
end
module act_low2
!q0,!q1 pin istype 'reg';
clock pin;
reset pin;
equations
[q1,q0].clk = clock;
[q1,q0] := ([q1,q0] + 1) & !reset;
test_vectors ([clock,reset] -> [ q1, q0])
[ .c. , 1 ] -> [ 0 , 0 ];
[ .c. , 0 ] -> [ 0 , 1 ];
[ .c. , 0 ] -> [ 1 , 0 ];
[ .c. , 0 ] -> [ 1 , 1 ];
[ .c. , 0 ] -> [ 0 , 0 ];
[ .c. , 0 ] -> [ 0 , 1 ];
[ .c. , 1 ] -> [ 0 , 0 ];
end
module DECLARE
declare device 'P16V8C';
A,B,Out1 pin 1,2,15;
Equations
Out1 = A & B;
Declarations
C,D,E,F,Out2 pin 3,4,5,6,16;
Temp1 = C & D;
Temp2 = E & F;
Equations
Out2 = Temp1 # Temp2;
end;
module detail1
d1 device 'P16R8';
Clk pin 1;
Toggle pin 2;
Ena pin 11;
Qout pin 19 istype 'reg_D';
equations
!Qout.D = Qout.Q & Toggle;
Qout.CLK = Clk;
Qout.OE = !Ena;
test_vectors([Clk,Ena,Toggle] -> [Qout])
[.c., 0 , 0 ] -> 0;
[.c., 0 , 1 ] -> 1;
[.c., 0 , 1 ] -> 0;
[.c., 0 , 1 ] -> 1;
[.c., 0 , 1 ] -> 0;
[.c., 1 , 1 ] -> .Z.;
[ 0 , 0 , 1 ] -> 1;
[.c., 1 , 1 ] -> .Z.;
[ 0 , 0 , 1 ] -> 0;
end
module detail2
d2 device 'E0320';
Clk pin 1;
Toggle pin 2;
Ena pin 11;
Qout pin 19 istype 'reg_D';
equations
Qout.D = !Qout.Q & Toggle;
Qout.CLK = Clk;
Qout.OE = !Ena;
test_vectors([Clk,Ena,Toggle] -> [Qout])
[.c., 0 , 0 ] -> 0;
[.c., 0 , 1 ] -> 1;
[.c., 0 , 1 ] -> 0;
[.c., 0 , 1 ] -> 1;
[.c., 0 , 1 ] -> 0;
[.c., 1 , 1 ] -> .Z.;
[ 0 , 0 , 1 ] -> 1;
[.c., 1 , 1 ] -> .Z.;
[ 0 , 0 , 1 ] -> 0;
end
module foo_1
foo pin istype 'reg';
Clock,Preset pin;
equations
foo.clk = Clock;
foo := !foo.fb # Preset;
test_vectors ([Clock,Preset] -> foo)
[ .c. , 1 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 0 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 1 ] -> 1;
[ .c. , 1 ] -> 1;
end
module foo_2
foo pin istype 'reg_D,buffer';
Clock,Preset pin;
equations
foo.CLK = Clock;
foo.D = !foo.Q # Preset;
test_vectors ([Clock,Preset] -> foo)
[ .c. , 1 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 0 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 1 ] -> 1;
[ .c. , 1 ] -> 1;
end
module foo_3
foo pin istype 'reg_D,invert';
Clock,Preset pin;
equations
foo.CLK = Clock;
!foo.D = foo.Q # Preset;
test_vectors ([Clock,Preset] -> foo)
[ .c. , 1 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 0 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 1 ] -> 1;
[ .c. , 1 ] -> 1;
end
module foo_5
foo pin istype 'reg,buffer';
Clock,Preset pin;
equations
foo.CLK = Clock;
foo.AP = Preset;
foo := !foo.fb ;
test_vectors ([Clock,Preset] -> foo)
[ .c. , 1 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 0 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 1 ] -> 1;
[ .c. , 1 ] -> 1;
end
module foo_7
foo pin istype 'reg,invert';
Clock,Preset pin;
equations
foo.CLK = Clock;
foo.AR = Preset;
foo := !foo.fb ;
test_vectors ([Clock,Preset] -> foo)
[ .c. , 1 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 0 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 1 ] -> 1;
[ .c. , 1 ] -> 1;
end
module par_det
title 'Architecture independent description of a serial parity detector.
SmartPart is required.
Jeff Davis Data I/O Corp. May 17,1990 '
Declarations
clock pin ;
serial_in pin ;
odd_even pin ;
shift pin ;
parity pin istype 'reg';
ODD = 1;
EVEN = 0;
Equations
parity.clk = clock; "Describe clocked input to register
"toggle parity when odd/even = EVEN and serial_in = 0
" and when odd/even = ODD and serial_in = 1
parity := ((serial_in !$ odd_even) & shift) $ parity.FB ;
Test_Vectors([clock,serial_in,odd_even,shift]->[parity])
[ .c. , 0 , EVEN , 0 ]->[ .X. ];
[ .c. , 1 , EVEN , 1 ]->[ EVEN ];
[ .c. , 0 , EVEN , 1 ]->[ ODD ];
[ .c. , 1 , EVEN , 1 ]->[ ODD ];
[ .c. , 1 , EVEN , 1 ]->[ ODD ];
[ .c. , 0 , EVEN , 1 ]->[ EVEN ];
[ .c. , 1 , ODD , 1 ]->[ ODD ];
[ .c. , 0 , ODD , 1 ]->[ ODD ];
[ .c. , 1 , ODD , 1 ]->[ EVEN ];
[ .c. , 0 , ODD , 1 ]->[ EVEN ];
[ .c. , 1 , ODD , 1 ]->[ ODD ];
[ .c. , 1 , EVEN , 0 ]->[ .X. ];
end
module pin2pin
Clk pin 1;
Toggle pin 2;
Ena pin 11;
Qout pin 19 istype 'reg';
equations
Qout := !Qout.FB & Toggle;
Qout.CLK = Clk;
Qout.OE = !Ena;
test_vectors([Clk,Ena,Toggle] -> [Qout])
[.c., 0 , 0 ] -> 0;
[.c., 0 , 1 ] -> 1;
[.c., 0 , 1 ] -> 0;
[.c., 0 , 1 ] -> 1;
[.c., 0 , 1 ] -> 0;
[.c., 1 , 1 ] -> .Z.;
[ 0 , 0 , 1 ] -> 1;
[.c., 1 , 1 ] -> .Z.;
[ 0 , 0 , 1 ] -> 0;
end
module sm1
q0,q1 pin istype 'reg'; "state registers
clock pin; "global clock input
start pin; "initialization input
A,B pin istype 'com'; "combinatorial outputs
equations
[q1,q0].clk = clock;
state_diagram [q1,q0]
state [1,1]:
A = 1; "A is high in this state
B = 1; "B is high in this state
if (start)
then [1,1]
else
[0,0];
state [1,0]:
A = 1; "A is high in this state
if (start)
then [1,1]
else
[0,1];
state [0,0]:
if (start)
then [1,1]
else
[0,1];
state [0,1]:
B = 1; "B is high in this state
goto [1,1];
test_vectors([clock,start]->[q1,q0])
[ .c. , 1 ]->[ 1, 1];
[ .c. , 0 ]->[ 0, 0];
[ .c. , 0 ]->[ 0, 1];
[ .c. , 0 ]->[ 1, 1];
[ .c. , 1 ]->[ 1, 1];
[ .c. , 0 ]->[ 0, 0];
[ .c. , 0 ]->[ 0, 1];
[ .c. , 1 ]->[ 1, 1];
end
module sm2
q0,q1 pin istype 'reg'; "state registers
clock pin; "global clock input
start pin; "initialization input
A,B pin istype 'com'; "combinatorial outputs
equations
[q1,q0].clk = clock;
truth_table ([q1.fb,q0.fb,start]:>[q1,q0]->[A,B])
[ 1 , 1 , 1 ]:>[ 1, 1]->[1,1];
[ 1 , 1 , 0 ]:>[ 0, 0]->[1,1];
[ 1 , 0 , 1 ]:>[ 1, 1]->[1,0];
[ 1 , 0 , 0 ]:>[ 0, 1]->[1,0];
[ 0 , 0 , 1 ]:>[ 1, 1]->[0,0];
[ 0 , 0 , 0 ]:>[ 0, 1]->[0,0];
[ 0 , 1 , 1 ]:>[ 1, 1]->[0,1];
[ 0 , 1 , 0 ]:>[ 1, 1]->[0,1];
test_vectors([clock,start]->[q1,q0])
[ .c. , 1 ]->[ 1, 1];
[ .c. , 0 ]->[ 0, 0];
[ .c. , 0 ]->[ 0, 1];
[ .c. , 0 ]->[ 1, 1];
[ .c. , 1 ]->[ 1, 1];
[ .c. , 0 ]->[ 0, 0];
[ .c. , 0 ]->[ 0, 1];
[ .c. , 1 ]->[ 1, 1];
end;
module source
options '-trace wave'
Title 'Example of a Source File
Lisa Matheson, Data I/O'
Declarations
dev1 DEVICE 'p16r4' ;
in1, in2, in3, clk PIN 2,3,4,5 ;
all, none, other PIN ISTYPE 'reg' ;
out = [all,none,other];
@MESSAGE 'Declarations completed'
Equations
out.clk = clk;
all := in1 & in2 & in3 ;
none := !in1 & !in2 & !in3 ;
other := (in1 & in2 & !in3) # (in1 & !in2 & in3)
# (in1 & !in2 & !in3) # (!in1 & in2 & in3)
# (!in1 & in2 & !in3) # (!in1 & !in2 & in3) ;
Test_Vectors
([in1,in2,in3,clk ] -> [all,none,other])
[ 1 , 1 , 1 ,.c. ] -> [ 1 , 0 , 0 ];
[ 0 , 1 , 1 ,.c. ] -> [ 0 , 0 , 1 ];
[ 1 , 0 , 0 ,.c. ] -> [ 0 , 0 , 1 ];
[ 1 , 0 , 1 ,.c. ] -> [ 0 , 0 , 1 ];
[ 0 , 0 , 0 ,.c. ] -> [ 0 , 1 , 0 ];
End source
module source2
Options '-trace wave'
Title 'Example of a device independent design; SmartPart is required
to run this example.
Lisa Matheson, Data I/O'
Declarations
dev1 DEVICE 'p16r4' ;
in1, in2, in3, clk PIN ;
all, none, other PIN ISTYPE 'reg' ;
out = [all,none,other];
@MESSAGE 'Declarations completed'
Equations
out.clk = clk;
all := in1 & in2 & in3 ;
none := !in1 & !in2 & !in3 ;
other := (in1 & in2 & !in3) # (in1 & !in2 & in3)
# (in1 & !in2 & !in3) # (!in1 & in2 & in3)
# (!in1 & in2 & !in3) # (!in1 & !in2 & in3) ;
Test_Vectors
([in1,in2,in3,clk ] -> [all,none,other])
[ 1 , 1 , 1 ,.c. ] -> [ 1 , 0 , 0 ];
[ 0 , 1 , 1 ,.c. ] -> [ 0 , 0 , 1 ];
[ 1 , 0 , 0 ,.c. ] -> [ 0 , 0 , 1 ];
[ 1 , 0 , 1 ,.c. ] -> [ 0 , 0 , 1 ];
[ 0 , 0 , 0 ,.c. ] -> [ 0 , 1 , 0 ];
End source2
module statema
title 'State machine example. Dave Pellerin';
clock,hold,reset pin;
P1,P0 pin istype 'reg';
P1,P0 istype 'buffer';
X = .x.;
equations
[P1,P0].clk = clock;
[P1,P0].ar = reset;
" state declarations...
declarations
stateA = [0,0];
stateB = [1,0];
stateC = [1,1];
stateD = [0,1];
state_diagram [P1,P0]
state stateA:
goto stateB;
state stateB:
goto stateC;
state stateC:
goto stateD;
state stateD:
goto stateA;
test_vectors([clock,reset]->[P1,P0])
[ .c. , 1 ]-> stateA;
[ .c. , 0 ]-> stateB;
[ .c. , 0 ]-> stateC;
[ .c. , 0 ]-> stateD;
[ .c. , 0 ]-> stateA;
[ .c. , 1 ]-> stateA;
end
module TT1
a,b,c pin; "design inputs
AND,OR pin istype 'com'; "combinatorial outputs
truth_table ([a,b,c]->[AND,OR])
[0,0,0]->[ 0 , 0];
[0,0,1]->[ 0 , 1];
[0,1,0]->[ 0 , 1];
[0,1,1]->[ 0 , 1];
[1,0,0]->[ 0 , 1];
[1,0,1]->[ 0 , 1];
[1,1,0]->[ 0 , 1];
[1,1,1]->[ 1 , 1];
end
module X1
foo pin istype 'com,xor';
a,b,c pin;
equations
foo = a $ b & c;
end
module X2
q3,q2,q1,q0 pin istype 'reg,xor';
clock pin;
count = [q3..q0];
equations
count.clk = clock;
count := count + 1;
end
module XORfact
xorfact device 'P20X10';
Clk,OE pin 1,13;
A,B,C,D pin 2,3,4,5;
Q16 pin 16;
XOR_Factors
Q16 := A & B;
equations
!Q16 := A & B & !D
# !B & C & D
# !A & C & D
# A & B & !C;
end
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