demo32.abl

自己编写的GAL可编程逻辑电路的编译软件abel4的windows界面

module DEMO32  
title 'Buried register example
Micheal Holley  Data I/O Corp  26 July 1990'

        demo32   device 'p32vx10';

" ABEL uses two device files to support the 32VX10.
" The P32VX10 ignores the programmable polarity after the register
" and depends on the XOR term for inversion.  The P32VX10 file has 
" programmable polarity for both registered and combinatorial outputs.
" The P32VX10A uses the output polarity fuse.
"
" Using the combintorial assigment (=) will cause the .FC term to be
" programmed for register bypass.
"
        clk,clr,cnt,ena pin  1,2,3,4;
        Q1,Q0           pin 14,15 istype 'invert';
        F1,F0           pin 16,17 ;
 
        C,X,Z = .C.,.X.,.Z.;

        StateReg  = [Q1,Q0];
        BufferIn  = [Q1,Q0];
        BufferOut = [F1,F0];

" The ABEL 4.0 state_diagram syntax defaults to .FB which is the 
" internal feedback path on devices with dual feedback.  

State_Diagram StateReg

        state 0: if (cnt) then 1 else 0;
        state 1: if (cnt) then 2 else 1;
        state 2: if (cnt) then 3 else 2;
        state 3: if (cnt) then 0 else 3;

Equations

     StateReg.OE  = !ena; 
     StateReg.Clk = clk; 
     StateReg.PR  = clr;         "Inverter after register

" The state machine counter does not depend on the pin feedback or
" the output enable.  When the output is disabled, (High Z) the pins
" may be used for inputs.

Equations

     BufferOut   = BufferIn;

Test_Vectors
             ([clk,ena,clr,cnt] ->StateReg)
              [ C , 0 , 1 , 1 ] ->   0; "Clear
              [ C , 0 , 0 , 1 ] ->   1; "Count
              [ C , 0 , 0 , 1 ] ->   2;
              [ C , 0 , 0 , 1 ] ->   3;
              [ C , 0 , 0 , 0 ] ->   3; "Hold
              [ C , 0 , 0 , 1 ] ->   0;
              [ C , 0 , 0 , 1 ] ->   1;
              [ C , 1 , 0 , 1 ] ->   Z; "Test for reg feedback
              [ 0 , 0 , 0 , 1 ] ->   2;
              [ C , 0 , 0 , 1 ] ->   3;
              [ C , 0 , 1 , 1 ] ->   0; "Clear

Test_Vectors
             ([clk,ena,clr,cnt,BufferIn] -> [StateReg,BufferOut])
              [ C , 0 , 1 , 1 ,   X    ] -> [   0    ,    0    ]; "Clear
              [ C , 0 , 0 , 1 ,   X    ] -> [   1    ,    1    ]; "Count
              [ C , 0 , 0 , 1 ,   X    ] -> [   2    ,    2    ];
              [ C , 0 , 0 , 1 ,   X    ] -> [   3    ,    3    ];
              [ C , 0 , 0 , 0 ,   X    ] -> [   3    ,    3    ]; "Hold
              [ C , 0 , 0 , 1 ,   X    ] -> [   0    ,    0    ];
              [ C , 0 , 0 , 1 ,   X    ] -> [   1    ,    1    ];

              [ 0 , 1 , 0 , 1 ,   X    ] -> [   Z    ,    X    ]; 
              [ 0 , 1 , 0 , 1 ,   3    ] -> [   X    ,    3    ]; 
              [ C , 1 , 0 , 1 ,   2    ] -> [   X    ,    2    ]; 
              [ C , 1 , 0 , 1 ,   1    ] -> [   X    ,    1    ]; 
              [ 0 , 1 , 0 , 1 ,   0    ] -> [   X    ,    0    ]; 
 
              [ C , 0 , 1 , 1 ,   X    ] -> [   0    ,    0    ]; "Clear
              [ C , 0 , 0 , 1 ,   X    ] -> [   1    ,    1    ]; "Count
              [ 0 , 1 , 0 , 1 ,   3    ] -> [   X    ,    3    ]; "Buffer
              [ 0 , 0 , 0 , 1 ,   X    ] -> [   X    ,    1    ]; "Count
              [ C , 0 , 0 , 1 ,   X    ] -> [   X    ,    2    ]; "Count
              [ 0 , 1 , 0 , 1 ,   0    ] -> [   X    ,    0    ]; "Buffer

End


module DEMO32a  
title 'Buried register example
Micheal Holley  Data I/O Corp  26 July 1990'

        demo32a   device 'p32vx10a';

" ABEL uses two device files to support the 32VX10.
"
" The P32VX10 ignores the programmable polarity after the register
" and depends on the XOR term for inversion.  The P32VX10 file has 
" programmable polarity for both registered and combinatorial outputs.
"
" The P32VX10A controls the programmable inverter with the 'buffer' or
" 'invert' attribute. Note that the combinatorial bypass is always inverted.
"
" Using the combinatorial assigment (=) will cause the .FC term to be
" programmed for register bypass.
"

        clk,clr,cnt,ena pin  1,2,3,4;
        Q1,Q0           pin 14,15 istype 'buffer';
        F1,F0           pin 16,17 istype 'invert';
 
        C,X,Z = .C.,.X.,.Z.;

        StateReg  = [Q1,Q0];
        BufferIn  = [Q1,Q0];
        BufferOut = [F1,F0];

" The ABEL 4.0 state_diagram syntax defaults to .FB which is the 
" internal feedback path on devices with dual feedback.  

State_Diagram StateReg

        state 0: if (cnt) then 1 else 0;
        state 1: if (cnt) then 2 else 1;
        state 2: if (cnt) then 3 else 2;
        state 3: if (cnt) then 0 else 3;

Equations

     StateReg.OE  = !ena; 
     StateReg.Clk = clk; 
     StateReg.sr  = clr;         "Buffer after register

" The state machine counter does not depend on the pin feedback or
" the output enable.  When the output is disabled, (High Z) the pins
" may be used for inputs.

Equations

     BufferOut   = BufferIn;

Test_Vectors
             ([clk,ena,clr,cnt] ->StateReg)
              [ C , 0 , 1 , 1 ] ->   0; "Clear
              [ C , 0 , 0 , 1 ] ->   1; "Count
              [ C , 0 , 0 , 1 ] ->   2;
              [ C , 0 , 0 , 1 ] ->   3;
              [ C , 0 , 0 , 0 ] ->   3; "Hold
              [ C , 0 , 0 , 1 ] ->   0;
              [ C , 0 , 0 , 1 ] ->   1;
              [ C , 1 , 0 , 1 ] ->   Z; "Test for reg feedback
              [ 0 , 0 , 0 , 1 ] ->   2;
              [ C , 0 , 0 , 1 ] ->   3;
              [ C , 0 , 1 , 1 ] ->   0; "Clear

Test_Vectors
             ([clk,ena,clr,cnt,BufferIn] -> [StateReg,BufferOut])
              [ C , 0 , 1 , 1 ,   X    ] -> [   0    ,    0    ]; "Clear
              [ C , 0 , 0 , 1 ,   X    ] -> [   1    ,    1    ]; "Count
              [ C , 0 , 0 , 1 ,   X    ] -> [   2    ,    2    ];
              [ C , 0 , 0 , 1 ,   X    ] -> [   3    ,    3    ];
              [ C , 0 , 0 , 0 ,   X    ] -> [   3    ,    3    ]; "Hold
              [ C , 0 , 0 , 1 ,   X    ] -> [   0    ,    0    ];
              [ C , 0 , 0 , 1 ,   X    ] -> [   1    ,    1    ];

              [ 0 , 1 , 0 , 1 ,   X    ] -> [   Z    ,    X    ]; 
              [ 0 , 1 , 0 , 1 ,   3    ] -> [   X    ,    3    ]; 
              [ C , 1 , 0 , 1 ,   2    ] -> [   X    ,    2    ]; 
              [ C , 1 , 0 , 1 ,   1    ] -> [   X    ,    1    ]; 
              [ 0 , 1 , 0 , 1 ,   0    ] -> [   X    ,    0    ]; 
 
              [ C , 0 , 1 , 1 ,   X    ] -> [   0    ,    0    ]; "Clear
              [ C , 0 , 0 , 1 ,   X    ] -> [   1    ,    1    ]; "Count
              [ 0 , 1 , 0 , 1 ,   3    ] -> [   X    ,    3    ]; "Buffer
              [ 0 , 0 , 0 , 1 ,   X    ] -> [   X    ,    1    ]; "Count
              [ C , 0 , 0 , 1 ,   X    ] -> [   X    ,    2    ]; "Count
              [ 0 , 1 , 0 , 1 ,   0    ] -> [   X    ,    0    ]; "Buffer

End