📄 f2407regs.h
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; Originator: Texas Instruments
;
; Description: F240 Header file containing all peripheral register
; declarations as well as other useful definitions.
;
; Last Updated: 27 May 1997
;
;***********************************************************************
;-----------------------------------------------------------------------
; On Chip Periperal Register Definitions (All registers mapped into data
; space unless otherwise noted)
;-----------------------------------------------------------------------
;Global memory and CPU interupt Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
IMR .set 0004h ;Interrupt Mask Register
GREG .set 0005h ;Global memory allocation Register
IFR .set 0006h ;Interrupt Flag Register
;System Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PIRQR0 .set 07010h
PIRQR1 .set 07011h
PIRQR2 .set 07012h
PIACKR0 .set 07014h
PIACKR1 .set 07015h
PIACKR2 .set 07016h
SCSR1 .set 07018h ;System Module Control Register
SCSR2 .set 07019h ;System Module Control Register
DINR .set 0701Ch ;System Module Status Register
PIVR .set 0701Eh ;System Interrupt Vector Register
;WD Control Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
WDCNTR .set 07023h ;WD Counter Register
WDKEY .set 07025h ;WD Key Register
WDCR .set 07029h ;WD Control register
;Serial Peripheral Interface (SPI) Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SPICCR .set 07040h ;SPI Configuration Control Register
SPICTL .set 07041h ;SPI Operation Control Register
SPISTS .set 07042h ;SPI Status Register
SPIBRR .set 07044h ;SPI Baud Rate Register
SPIEMU .set 07046h ;SPI Emulation buffer Register
SPIRXBUF .set 07047h ;SPI Serial Input Buffer register
SPITXBUF .set 07048h ;SPI Serial Input Buffer register
SPIDAT .set 07049h ;SPI Serial Data Register
SPIPRI .set 0704Fh ;SPI Priority control Register
;Serial Communications Interface (SCI) Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SCICCR .set 07050h ;SCI Communication Control Register
SCICTL1 .set 07051h ;SCI Control Register 1
SCIHBAUD .set 07052h ;SCI Baud Select register, high bits
SCILBAUD .set 07053h ;SCI Baud Select register, high bits
SCICTL2 .set 07054h ;SCI Control Register 2
SCIRXST .set 07055h ;SCI Receive Status Register
SCIRXEMU .set 07056h ;SCI Emulation data buffer Register
SCIRXBUF .set 07057h ;SCI Receiver data buffer Register
SCITXBUF .set 07059h ;SCI Transmit data buffer Register
SCIPRI .set 0705Fh ;SCI Priority Control register
;External Interrupt Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
XINT1CR .set 07070h ;Interrupt 1 Control Register
XINT2CR .set 07071h ;Interrupt 2 Control register
;Digital I/O Control Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
MCRA .set 07090h ;Output Control Reg A
MCRB .set 07092h ;Output Control Reg B
MCRC .set 07094h ;Output Control Reg C
PEDATDIR .set 07095h ;I/O port E Data & Direction reg.
PFDATDIR .set 07096h ;I/O port F Data & Direction reg.
PADATDIR .set 07098h ;I/O port A Data & Direction reg.
PBDATDIR .set 0709Ah ;I/O port B Data & Direction reg.
PCDATDIR .set 0709Ch ;I/O port C Data & Direction reg.
PDDATDIR .set 0709Eh ;I/O port D Data & Direction reg.
;Analog-to-Digital Converter(ADC) registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ADCCTRL1 .set 070A0h ;ADC Control Register 1
ADCCTRL2 .set 070A1h ;ADC Control Register 2
MAXCONV .set 070A2h ;
CHSELSEQ1 .set 070A3h ;
CHSELSEQ2 .set 070A4h ;
CHSELSEQ3 .set 070A5h ;
CHSELSEQ4 .set 070A6h ;
AUTO_SEQ_SR .set 070A7h ;
RESULT0 .set 070A8h ;Result register0
RESULT1 .set 070A9h ;Result register1
RESULT2 .set 070AAh ;Result register2
RESULT3 .set 070ABh ;Result register3
RESULT4 .set 070ACh ;Result register4
RESULT5 .set 070ADh ;Result register5
RESULT6 .set 070AEh ;Result register6
RESULT7 .set 070AFh ;Result register7
RESULT8 .set 070B0h ;Result register8
RESULT9 .set 070B1h ;Result register9
RESULT10 .set 070B2h ;Result register10
RESULT11 .set 070B3h ;Result register11
RESULT12 .set 070B4h ;Result register12
RESULT13 .set 070B5h ;Result register13
RESULT14 .set 070B6h ;Result register14
RESULT15 .set 070B7h ;Result register15
CALIBRATION .set 070B8h ;
;CAN Configuration Control Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
MDER .set 07100h ;
TCR .set 07101h ;
RCR .set 07102h ;
MCR .set 07103h ;
BCR2 .set 07104h ;
BCR1 .set 07105h ;
ESR .set 07106h ;
GSR .set 07107h ;
CEC .set 07108h ;
CAN_IFR .set 07109h ;
CAN_IMR .set 0710Ah ;
LAM0_H .set 0710Bh ; YLP NOTICE
LAM0_L .set 0710Ch ;
LAM1_H .set 0710Dh ;
LAM1_L .set 0710Eh ;
; Message Objects#0
MSGID0L .set 07200h ;
MSGID0H .set 07201h ;
MSGCTRL0 .set 07202h ;
MBX0A .set 07204h ;
MBX0B .set 07205h ;
MBX0C .set 07206h ;
MBX0D .set 07207h ;
; Message Objects#1
MSGID1L .set 07208h ;
MSGID1H .set 07209h ;
MSGCTRL1 .set 0720Ah ;
MBX1A .set 0720Ch ;
MBX1B .set 0720Dh ;
MBX1C .set 0720Eh ;
MBX1D .set 0720Fh ;
; Message Objects#2
MSGID2L .set 07210h ;
MSGID2H .set 07211h ;
MSGCTRL2 .set 07212h ;
MBX2A .set 07214h ;
MBX2B .set 07215h ;
MBX2C .set 07216h ;
MBX2D .set 07217h ;
; Message Objects#3
MSGID3L .set 07218h ;
MSGID3H .set 07219h ;
MSGCTRL3 .set 0721Ah ;
MBX3A .set 0721Ch ;
MBX3B .set 0721Dh ;
MBX3C .set 0721Eh ;
MBX3D .set 0721Fh ;
; Message Objects#4
MSGID4L .set 07220h ;
MSGID4H .set 07221h ;
MSGCTRL4 .set 07222h ;
MBX4A .set 07224h ;
MBX4B .set 07225h ;
MBX4C .set 07226h ;
MBX4D .set 07227h ;
; Message Objects#5
MSGID5L .set 07228h ;
MSGID5H .set 07229h ;
MSGCTRL5 .set 0722Ah ;
MBX5A .set 0722Ch ;
MBX5B .set 0722Dh ;
MBX5C .set 0722Eh ;
MBX5D .set 0722Fh ;
;General Purpose Timer Registers - Event Manager (EVA)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
GPTCONA .set 7400h ;General Purpose Timer Control Register
T1CNT .set 7401h ;GP Timer 1 Counter Register
T1CMPR .set 7402h ;GP Timer 1 Compare Register
T1PR .set 7403h ;GP Timer 1 Period Register
T1CON .set 7404h ;GP Timer 1 Control Register
T2CNT .set 7405h ;GP Timer 2 Counter Register
T2CMPR .set 7406h ;GP Timer 2 Compare Register
T2PR .set 7407h ;GP Timer 2 Period Register
T2CON .set 7408h ;GP Timer 2 Control Register
;Full & Simple Compare Unit Registers - Event Manager (EVA)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
COMCONA .set 7411h ;Compare Control register A
ACTRA .set 7413h ;Full Compare Action Control register A
DBTCONA .set 7415h ;Dead-band Timer Control register A
CMPR1 .set 7417h ;Full Compare Unit 1 Compare Register
CMPR2 .set 7418h ;Full Compare Unit 2 Compare Register
CMPR3 .set 7419h ;Full Compare Unit 3 Compare Register
;Capture & QEP Registers - Event Manager (EVA)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
CAPCONA .set 7420h ;Capture Control register A
CAPFIFOA .set 7422h ;Capture FIFO Status register A
CAP1FIFO .set 7423h ;Capture 1 Two-level deep FIFO Register
CAP2FIFO .set 7424h ;Capture 2 Two-level deep FIFO Register
CAP3FIFO .set 7425h ;Capture 3 Two-level deep FIFO Register
CAP1FBOT .set 7427h ;
CAP2FBOT .set 7428h ;
CAP3FBOT .set 7429h ;
; Event Manager (EVA) Interrupt Control Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
EVAIMRA .set 742Ch ;EV Interrupt Mask Register A
EVAIMRB .set 742Dh ;EV Interrupt Mask Register B
EVAIMRC .set 742Eh ;EV Interrupt Mask Register C
EVAIFRA .set 742Fh ;EV Interrupt Flag Register A
EVAIFRB .set 7430h ;EV Interrupt Flag Register B
EVAIFRC .set 7431h ;EV Interrupt Flag Register C
;General Purpose(GP) Timer Configuration Control Registers-EVB
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
GPTCONB .set 7500h ;
T3CNT .set 7501h ;
T3CMPR .set 7502h ;
T3PR .set 7503H ;
T3CON .set 7504h ;
T4CNT .set 7505h ;
T4CMPR .set 7506h ;
T4PR .set 7507H ;
T4CON .set 7508h ;
;Full And Simple Compare Unit Registers-EVB
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
COMCONB .set 7511h ;
ACTRB .set 7513h ;
DBTCONB .set 07515h ;
CMPR4 .set 07517h ;
CMPR5 .set 07518h ;
CMPR6 .set 07519h ;
;Capture Unit Registers -EVB
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
CAPCONB .set 7520h ;
CAPFIFOB .set 7522h ;
CAP4FIFO .set 7523h ;
CAP5FIFO .set 7524h ;
CAP6FIFO .set 7525h ;
CAP4FBOT .set 7527h ;
CAP5FBOT .set 7528h ;
CAP6FBOT .set 7529h ;
; Event Manager (EVB) Interrupt Control Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
EVBIMRA .set 742Ch ;EV Interrupt Mask Register A
EVBIMRB .set 742Dh ;EV Interrupt Mask Register B
EVBIMRC .set 742Eh ;EV Interrupt Mask Register C
EVBIFRA .set 742Fh ;EV Interrupt Flag Register A
EVBIFRB .set 7430h ;EV Interrupt Flag Register B
EVBIFRC .set 7431h ;EV Interrupt Flag Register C
;Program Memory Space -Flash Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;PMPC .set 0h ;Flash Segment Control Register
;CTRL .set 01h ;
;WADDR .set 2h ;Flash Write Address Register
;WDATA .set 3h ;Flash Write Data register
;TCR .set 4h ;
;ENAB .set 5h ;
;SETC .set 6h ;
;I/O Memory Space
FCMR .set 0FF0Fh ;
;Wait State Generator Registers (mapped into I/O space)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
WSGR .set 0FFFFh ;Wait State Generator register
;Data Memory Boundary Addresses
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
B0_SADDR .set 00200h ;Block B0 start address
B0_EADDR .set 002FFh ;Block B0 end address
B1_SADDR .set 00400h ;Block B1 start address
B1_EADDR .set 004FFh ;Block B1 end address
B2_SADDR .set 00060h ;Block B2 start address
B2_EADDR .set 0007Fh ;Block B2 end address
XDATA_SADDR .set 08000h ;External Data Space start address
XDATA_EADDR .set 0FFFFh ;External Data Space end address
;Frequently Used Data Pages
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
DP_B2 .set 0 ;page 0 of data space
DP_B01 .set 4 ;page 4 of B0(200H/80H)
DP_B02 .set 5 ;page 5 of B0(280H/80H)
DP_B11 .set 6 ;page 6 of B1(300H/80H)
DP_B12 .set 7 ;page 7 of AD(380H/80H)
DP_SARAM1 .set 16 ;page 1 of SARAM(800h/80h)
DP_SARAM2 .set 17 ;page 2 of SARAM(880h/80h)
DP_SARAM3 .set 18 ;page 3 of SARAM(900h/80h)
DP_SARAM4 .set 19 ;page 4 of SARAM(980h/80h)
DP_PF1 .set 224 ;page 1 of Peripheral Frame1 file (7000h/80h)(0XE0)
DP_PF2 .set 225 ;page 2 of Peripheral Frame1 file (7080h/80h)(0XE1)
DP_CAN .set 226 ;page 3 of Peripheral Frame1 file (7100h/80h)(0XE2)
DP_PF4 .set 227 ;page 4 of Peripheral Frame1 file (7080h/80h)(0XE3)
DP_CAN2 .set 228 ;page 5 of Peripheral Frame1 file (7200h/80h)(0XE4)
DP_EVA .set 232 ;page 0 of Event Manager-EVA file (7400h/80h)(0xE8)
DP_EVB .set 234 ;page 0 of Event Manager-EVB file (7500h/80h)(0xE9)
;Bit codes for Test Bit instruction (BIT)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
BIT15 .set 0000h ;Bit Code for 15
BIT14 .set 0001h ;Bit Code for 14
BIT13 .set 0002h ;Bit Code for 13
BIT12 .set 0003h ;Bit Code for 12
BIT11 .set 0004h ;Bit Code for 11
BIT10 .set 0005h ;Bit Code for 10
BIT9 .set 0006h ;Bit Code for 9
BIT8 .set 0007h ;Bit Code for 8
BIT7 .set 0008h ;Bit Code for 7
BIT6 .set 0009h ;Bit Code for 6
BIT5 .set 000Ah ;Bit Code for 5
BIT4 .set 000Bh ;Bit Code for 4
BIT3 .set 000Ch ;Bit Code for 3
BIT2 .set 000Dh ;Bit Code for 2
BIT1 .set 000Eh ;Bit Code for 1
BIT0 .set 000Fh ;Bit Code for 0
;Bit masks used by the SBIT0 & SBIT1 Macros
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
B15_MSK .set 8000h ;Bit Mask for 15
B14_MSK .set 4000h ;Bit Mask for 14
B13_MSK .set 2000h ;Bit Mask for 13
B12_MSK .set 1000h ;Bit Mask for 12
B11_MSK .set 0800h ;Bit Mask for 11
B10_MSK .set 0400h ;Bit Mask for 10
B9_MSK .set 0200h ;Bit Mask for 9
B8_MSK .set 0100h ;Bit Mask for 8
B7_MSK .set 0080h ;Bit Mask for 7
B6_MSK .set 0040h ;Bit Mask for 6
B5_MSK .set 0020h ;Bit Mask for 5
B4_MSK .set 0010h ;Bit Mask for 4
B3_MSK .set 0008h ;Bit Mask for 3
B2_MSK .set 0004h ;Bit Mask for 2
B1_MSK .set 0002h ;Bit Mask for 1
B0_MSK .set 0001h ;Bit Mask for 0
;-----------------------------------------------------------------------
; M A C R O - Definitions
;-----------------------------------------------------------------------
SBIT0 .macro DMA, MASK ;Clear bit Macro
LACC DMA
AND #(0FFFFh-MASK)
SACL DMA
.endm
SBIT1 .macro DMA, MASK ;Set bit Macro
LACC DMA
OR #(MASK)
SACL DMA
.endm
KICK_DOG .macro ;Watchdog reset macro
LDP #00E0h ;DP-->7000h-707Fh
SPLK #05555h, WDKEY ;WDCNTR is enabled to be reset by next AAh
SPLK #0AAAAh, WDKEY ;WDCNTR is reset
.endm
DELAY_S .macro delay_value ;delay = 0.05uS x delay_value
RPT #delay_value
NOP
.endm
;---------------------------------------------------------------------
; Users define
;---------------------------------------------------------------------
;Variable definitions
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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