📄 bldc3_21.lst
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557
558 ;===========================================================================================
559 007f MAIN: ;Main system background loop
560 ;===========================================================================================
561 007f 7980 M_1 B M_1
0080 007f'
562 ;===========================================================================================
563
564 ;-------------------------------------------------------------------------------------------
565 ;T2PR Interrupt Service Routine
566 ;-------------------------------------------------------------------------------------------
567 0081 T2_PERIOD_ISR:
568 ;Context save regs
569 0081 8b89 MAR *,AR1 ;AR1 is stack pointer
570 0082 8ba0 MAR *+ ;skip one position
571 0083 8fa0 SST #1, *+ ;save ST1
572 0084 8ea0 SST #0, *+ ;save ST0
573 0085 98a0 SACH *+ ;save acc high
574 0086 90a0 SACL *+ ;save acc low
575 0087 86a0 SAR AR6,*+ ;save AR6
576 0088 8580 SAR AR5,* ;save AR5
577
578 0089 POINT_EV
1 0089 bce8 LDP #0E8h
579 008a ae30 SPLK #0FFFFh,IFRB ; Clear all Group B interrupt flags (T2 ISR)
008b ffff
580
TMS320C24xx COFF Assembler Version 7.02 Mon Apr 28 11:35:36 2003
Copyright (c) 1987-2002 Texas Instruments Incorporated
bldc3_21.asm PAGE 13
581 ;Start main section of ISR
582 008c POINT_B0
1 008c bc04 LDP #04h
583
584 ; verifying the ISR
585 008d 100e- LACC isr_ticker
586 008e b801 ADD #1
587 008f 900e- SACL isr_ticker
588
589 ;-------------------------------------------------------------------------------------------
590 ;Rotor alignment phase
591 ;----------------------------------------
592 0090 POINT_B0
1 0090 bc04 LDP #04h
593 0091 1008- lacc align_flag
594 0092 e388 bcnd RUN_MODE, EQ
0093 00af'
595
596 0094 bc00! ldp #m6_cntr
597 0095 ae00! SPLK #0, m6_cntr
0096 0000
598 0097 bc00! ldp #cmtn_ptr_bd
599 0098 ae00! SPLK #0, cmtn_ptr_bd
0099 0000
600
601 009a 7a80 CALL BLDC_3PWM_DRV
009b 0000!
602
603 009c POINT_B0
1 009c bc04 LDP #04h
604 009d 1003- lacc v_timer
605 009e bfa0 sub #07FFEh ;wait for a "while"
009f 7ffe
606 00a0 e344 bcnd updat_v_timer, LT ;If not time out, stay in alignment mode
00a1 00c6'
607 00a2 100d- lacc loop_cnt
608 00a3 ba08 sub #LOOP_CNT_MAX
609 00a4 e388 bcnd CLR_ALGN_FLAG,EQ
00a5 00ad'
610 00a6 100d- lacc loop_cnt
611 00a7 b801 add #1
612 00a8 900d- sacl loop_cnt
613 00a9 ae03- splk #0, v_timer
00aa 0000
614 00ab 7980 B updat_v_timer
00ac 00c6'
615
616 00ad CLR_ALGN_FLAG
617 00ad ae08- splk #0, align_flag
00ae 0000
618
619
620 00af RUN_MODE
621
TMS320C24xx COFF Assembler Version 7.02 Mon Apr 28 11:35:36 2003
Copyright (c) 1987-2002 Texas Instruments Incorporated
bldc3_21.asm PAGE 14
622 ;SYSTEM INCREMENTAL BUILD OPTIONS
623 ;-------------------------------------------------------------------------------------------
624
625 .if (phase1_inc_build)
626
627 ;Open loop commutation control
628 ;-----------------------------
629
630 00af 7a80 CALL RMP3CNTL
00b0 0000!
631 00b1 POINT_B0
1 00b1 bc04 LDP #04h
632 00b2 a80a- bldd #rmp3_out, cmtn_period_setpt
00b3 0000!
633
634 00b4 bc00! ldp #ig_period
635 00b5 a800! bldd #rmp3_out, ig_period
00b6 0000!
636
637 00b7 7a80 CALL IMPULSE
00b8 0000!
638
639 00b9 bc00! ldp #m6_trig_in
640 00ba a800! bldd #ig_out, m6_trig_in
00bb 0000!
641
642 00bc 7a80 CALL MOD6_CNT
00bd 0000!
643
644 00be bc00! ldp #cmtn_ptr_bd
645 00bf a800! bldd #m6_cntr, cmtn_ptr_bd ;Input to BLDC_PWM_DRV
00c0 0000!
646 00c1 bc00! ldp #cmtn_ptr_ct
647 00c2 a800! bldd #m6_cntr, cmtn_ptr_ct ;Input to COMMUTATION_TRIGGER
00c3 0000!
648
649 00c4 7a80 CALL BLDC_3PWM_DRV
00c5 0000!
650
651 .endif
652 ;-------------------------------------------------------------------------------------------
653 ;-------------------------------------------------------------------------------------------
654 .if (phase2_inc_build)
655
656 ;Open loop commutation control
657 ;-----------------------------
658
659 CALL RMP3CNTL
660
661 POINT_B0
662 bldd #rmp3_out, cmtn_period_setpt
663
664 ldp #ig_period
665 bldd #rmp3_out, ig_period
TMS320C24xx COFF Assembler Version 7.02 Mon Apr 28 11:35:36 2003
Copyright (c) 1987-2002 Texas Instruments Incorporated
bldc3_21.asm PAGE 15
666
667
668 CALL IMPULSE
669
670 ldp #m6_trig_in
671 bldd #ig_out, m6_trig_in
672
673 CALL MOD6_CNT
674
675 ldp #cmtn_ptr_bd
676 bldd #m6_cntr, cmtn_ptr_bd ;Input to BLDC_PWM_DRV
677 ldp #cmtn_ptr_ct
678 bldd #m6_cntr, cmtn_ptr_ct ;Input to COMMUTATION_TRIGGER
679
680 CALL BLDC_3PWM_DRV
681 CALL ADC04U_DRV
682
683
684 ldp #Va
685 bldd #C1_out, Va
686 bldd #C2_out, Vb
687 bldd #C3_out, Vc
688
689 CALL COMTN_TRIG
690
691 .endif
692 ;-------------------------------------------------------------------------------------------
693 ;-------------------------------------------------------------------------------------------
694 .if (phase3_inc_build)
695
696 ;Open loop commutation control
697 ;-----------------------------
698
699 CALL RMP3CNTL
700
701 POINT_B0
702 bldd #rmp3_out, cmtn_period_setpt
703
704 ldp #ig_period
705 bldd #rmp3_out, ig_period
706
707
708 CALL IMPULSE
709
710 ldp #m6_trig_in
711 bldd #ig_out, m6_trig_in
712
713 CALL MOD6_CNT
714
715 ldp #cmtn_ptr_bd
716 bldd #m6_cntr, cmtn_ptr_bd ;Input to BLDC_PWM_DRV
717 ldp #cmtn_ptr_ct
718 bldd #m6_cntr, cmtn_ptr_ct ;Input to COMMUTATION_TRIGGER
719
TMS320C24xx COFF Assembler Version 7.02 Mon Apr 28 11:35:36 2003
Copyright (c) 1987-2002 Texas Instruments Incorporated
bldc3_21.asm PAGE 16
720 CALL BLDC_3PWM_DRV
721 CALL ADC04U_DRV
722
723 ldp #Va
724 bldd #C1_out, Va
725 bldd #C2_out, Vb
726 bldd #C3_out, Vc
727
728 CALL COMTN_TRIG
729
730 .endif
731 ;-------------------------------------------------------------------------------------------
732 ;-------------------------------------------------------------------------------------------
733 .if (phase4_inc_build)
734
735 ;Closed loop commutation control
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