📄 bldc3_21.lst
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370
371 POINT_B0
372 ;For open loop speed ramp control
373 SPLK #0200h, cmtn_period_target ;Final ramp speed
374 SPLK #500h, cmtn_period_setpt ;Init ramp starting point
375
376 SPLK #0400, ramp_delay ;Set ramp rate (higher val = slower ramp)
377
378 ;For open loop D_func control
379 SPLK #0h, I_loop_flg ;start with open loop current
380 SPLK #ALIGN_DUTY, D_func_desired
381
382 .endif
383
384 ;Motor aub
385 ;-----------------------------------
386 .if (aub)
387 ALIGN_DUTY .set 0F00h
388 LOOP_CNT_MAX .set 0
389
TMS320C24xx COFF Assembler Version 7.02 Mon Apr 28 11:35:36 2003
Copyright (c) 1987-2002 Texas Instruments Incorporated
bldc3_21.asm PAGE 9
390 POINT_B0
391 ;For open loop speed ramp control
392 SPLK #0200h, cmtn_period_target ;Final ramp speed (lower val = higher speed)
393 SPLK #500h, cmtn_period_setpt ;Init ramp starting point
394 SPLK #0400, ramp_delay ;Set ramp rate (higher val = slower ramp)
395
396 ;For open loop D_func control
397 SPLK #0h, I_loop_flg ;start with open loop current
398 SPLK #ALIGN_DUTY, D_func_desired ;set PWM duty cycle
399
400 .endif
401
402
403 ;Motor ads
404 ;------------------------------------
405 .if (ads)
406 ALIGN_DUTY .set 0F00h
407 LOOP_CNT_MAX .set 0
408
409 POINT_B0
410 ;For open loop speed ramp control
411 SPLK #0300h, cmtn_period_target ;Final commutation period
412 SPLK #500h, cmtn_period_setpt ;Initial commutation period
413
414 .if (x243)
415 SPLK #0200, ramp_delay ;Set ramp rate
416 .endif
417
418 .if (x2407)
419 SPLK #01000, ramp_delay
420 .endif
421
422 ;For open loop D_func control
423 SPLK #0h, I_loop_flg ;start with open loop current
424 SPLK #ALIGN_DUTY, D_func_desired
425
426 .endif
427
428
429 ;------------------------------------------------------------------------------------------
430 ;Other Parameters Initialization
431 ;------------------------------------------------------------------------------------------
432 004b POINT_B0
1 004b bc04 LDP #04h
433 004c ae0b- SPLK #0, sp_up_done_flg
004d 0000
434 004e ae08- SPLK #0Fh, align_flag
004f 000f
435 0050 ae03- SPLK #0,v_timer ;set virtual timer to start at zero.
0051 0000
436 0052 ae0d- SPLK #0,loop_cnt
0053 0000
437 ;------------------------------------------------------------------------------------------
438 ;Initial parameter passing to modules
TMS320C24xx COFF Assembler Version 7.02 Mon Apr 28 11:35:36 2003
Copyright (c) 1987-2002 Texas Instruments Incorporated
bldc3_21.asm PAGE 10
439 ;------------------------------------------------------------------------------------------
440 0054 bc00! ldp #rmp2_out
441 0055 ae00! SPLK #ALIGN_DUTY, rmp2_out
0056 3000
442 0057 ae00! SPLK #50h, rmp2_dly
0058 0050
443 0059 ae00! SPLK #07fffh, rmp2_max
005a 7fff
444 005b ae00! SPLK #0fh, rmp2_min
005c 000f
445
446 005d bc00! ldp #rmp3_desired
447 005e a800! bldd #cmtn_period_target, rmp3_desired
005f 0009-
448 0060 a800! bldd #ramp_delay, rmp3_dly
0061 000c-
449 0062 a800! bldd #cmtn_period_setpt, rmp3_out
0063 000a-
450 0064 ae00! SPLK #50h, rmp3_min
0065 0050
451
452 0066 bc00! ldp #D_func
453 0067 ae00! SPLK #ALIGN_DUTY, D_func
0068 3000
454
455 0069 bc00! ldp #NW_DYN_THOLD
456 006a ae00! splk #15, NW_DYN_THOLD
006b 000f
457 006c ae00! SPLK #2, cdnw_delta
006d 0002
458 006e 1000! LACC NW_DYN_THOLD
459 006f 3000! SUB cdnw_delta
460 0070 9000! SACL noise_window_max
461
462 0071 bc00! ldp #pid_out_reg2
463 0072 ae00! splk #7000h, pid_max_reg2 ;Q15
0073 7000
464 0074 ae00! splk #09000h, pid_min_reg2 ;Q15
0075 9000
465 0076 ae00! SPLK #0080h,K0_reg2 ;Q9
0077 0080
466 0078 ae00! SPLK #0140h,K1_reg2 ;Q13
0079 0140
467 007a ae00! SPLK #0506h,Kc_reg2 ;Q13
007b 0506
468
469
470
471
472 ;------------------------------------------------------------------------------------------
473 ;SYSTEM INCREMENTAL BUILD OPTIONS - Initialization
474 ;------------------------------------------------------------------------------------------
475 .if (phase1_inc_build)
476
TMS320C24xx COFF Assembler Version 7.02 Mon Apr 28 11:35:36 2003
Copyright (c) 1987-2002 Texas Instruments Incorporated
bldc3_21.asm PAGE 11
477 ;DAC pointer init
478 007c bc00! ldp #DAC_IPTR0
479 007d ae00! SPLK #ig_out, DAC_IPTR0
007e 0000!
480
481 .endif
482
483 ;-------------------------------------------------------------------------------------------
484 .if (phase2_inc_build)
485
486 ;ADC gain & offset adjustment
487 ldp #C1_gain
488 SPLK #0800h, C1_gain ;gain = 0.125 (Q13)
489 SPLK #0800h, C2_gain ;gain = 0.125 (Q13)
490 SPLK #0800h, C3_gain ;gain = 0.125 (Q13)
491 SPLK #1FFFh, C4_gain ;gain = 1.0 (Q13)
492
493 ;DAC pointer init
494 ldp #DAC_IPTR0
495 SPLK #C1_out, DAC_IPTR0
496 SPLK #C2_out, DAC_IPTR1
497 SPLK #C3_out, DAC_IPTR2
498 SPLK #C4_out, DAC_IPTR3
499
500 .endif
501 ;-------------------------------------------------------------------------------------------
502 ;-------------------------------------------------------------------------------------------
503 .if (phase3_inc_build)
504
505 ;ADC gain & offset adjustment
506 ldp #C1_gain
507 SPLK #0800h, C1_gain ;gain = 0.125 (Q13)
508 SPLK #0800h, C2_gain ;gain = 0.125 (Q13)
509 SPLK #0800h, C3_gain ;gain = 0.125 (Q13)
510 SPLK #1FFFh, C4_gain ;gain = 1.0 (Q13)
511
512
513 ;DAC pointer init
514 ldp #DAC_IPTR0
515 SPLK #cmtn_trig, DAC_IPTR0
516 SPLK #neutral, DAC_IPTR1
517 SPLK #zc_trig, DAC_IPTR2
518 SPLK #debug_Bemf, DAC_IPTR3
519
520 .endif
521 ;-------------------------------------------------------------------------------------------
522 ;-------------------------------------------------------------------------------------------
523 .if (phase4_inc_build)
524
525 ;ADC gain & offset adjustment
526 ldp #C1_gain
527 SPLK #0800h, C1_gain ;gain = 0.125 (Q13)
528 SPLK #0800h, C2_gain ;gain = 0.125 (Q13)
529 SPLK #0800h, C3_gain ;gain = 0.125 (Q13)
TMS320C24xx COFF Assembler Version 7.02 Mon Apr 28 11:35:36 2003
Copyright (c) 1987-2002 Texas Instruments Incorporated
bldc3_21.asm PAGE 12
530 SPLK #1FFFh, C4_gain ;gain = 1.0 (Q13)
531
532 .endif
533 ;-------------------------------------------------------------------------------------------
534 ;-------------------------------------------------------------------------------------------
535 .if (phase5_inc_build)
536
537 ;DAC pointer init
538 ldp #DAC_IPTR0
539 SPLK #cmtn_trig, DAC_IPTR0
540 SPLK #debug_Bemf, DAC_IPTR1
541
542 ;ADC gain & offset adjustment
543 ldp #C1_gain
544 SPLK #0800h, C1_gain ;gain = 0.125 (Q13)
545 SPLK #0800h, C2_gain ;gain = 0.125 (Q13)
546 SPLK #0800h, C3_gain ;gain = 0.125 (Q13)
547 SPLK #1FFFh, C4_gain ;gain = 1.0 (Q13)
548
549 POINT_B0
550 SPLK #0065h, current_set
551
552
553 .endif
554 ;-------------------------------------------------------------------------------------------
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