📄 bldc3_21.lst
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188 0016 7a80 CALL BC_INIT
0017 0000!
189 0018 7a80 CALL SPEED_REV_PRD_INIT
0019 0000!
190 ;------------------------------------------------------------------------------------------
191 ;System time-base init
192 ;------------------------------------------------------------------------------------------
193 ; Here time base is derived from T1 Underflow Int (i.e. Period)
194 ; in BLDC_3PWM_DRV module.
195
196 ;Initialize period register
TMS320C24xx COFF Assembler Version 7.02 Mon Apr 28 11:35:36 2003
Copyright (c) 1987-2002 Texas Instruments Incorporated
bldc3_21.asm PAGE 5
197 001a POINT_EV
1 001a bce8 LDP #0E8h
198 001b ae07 SPLK #SYSTEM_INT_PERIOD, T2PER
001c 03e8
199
200 ;5432109876543210
201 ;||||!!!!||||!!!!
202 001d ae08 SPLK #1001000001000000b, T2CON ;Asym
001e 9040
203
204 ;------------------------------------------------------------------------------------------
205 ; Initialise the Real time monitor
206 ;---Real Time enable---------------
207 .if (real_time)
208 001f 7a80 CALL MON_RT_CNFG ;For Real-Time
0020 0000!
209 .endif
210 ;------------------------------------------------------------------------------------------
211
212 ;------------------------------------------------------------------------------------------
213 ; System Interrupt Init.
214 ;------------------------------------------------------------------------------------------
215 ;Event Manager
216 0021 POINT_EV
1 0021 bce8 LDP #0E8h
217 ; SPLK #0000001000000000b,IMRA ;Enable T1 Underflow Int (i.e. Period)
218 0022 ae2d SPLK #0000000000000100b,IMRB ;Enable T2 Underflow Int (i.e. Period)
0023 0004
219 ; SPLK #0000000000000001b,IMRB
220 ; SPLK #0000000000000100b,IMRC ;Enable CAP3 int (i.e. QEP index pulse)
221 ;||||!!!!||||!!!!
222 ;5432109876543210
223
224 0024 ae2f SPLK #0FFFFh,IFRA ; Clear all Group A interrupt flags
0025 ffff
225 0026 ae30 SPLK #0FFFFh,IFRB ; Clear all Group B interrupt flags
0027 ffff
226 0028 ae31 SPLK #0FFFFh,IFRC ; Clear all Group C interrupt flags
0029 ffff
227
228 ;C2xx Core
229 002a POINT_PG0
1 002a bc00 LDP #00h
230
231 ;---Real Time enable------------------------------------------------------------------------
232 .if (real_time)
233 ; SPLK #0000000001000010b,IMR ;En Int lvl 2 & 7 (T1 ISR)
234 002b ae04 SPLK #0000000001000100b,IMR ;En Int lvl 3 & 7 (T2 ISR)
002c 0044
235 ;5432109876543210
236 .endif
237
238
239 .if (real_time != 1)
TMS320C24xx COFF Assembler Version 7.02 Mon Apr 28 11:35:36 2003
Copyright (c) 1987-2002 Texas Instruments Incorporated
bldc3_21.asm PAGE 6
240 ; SPLK #0000000000000010b,IMR ;En Int lvl 2 (T1 ISR)
241 SPLK #0000000000000100b,IMR ;En Int lvl 3 (T2 ISR)
242 ;||||!!!!||||!!!!
243 ;5432109876543210
244 .endif
245
246 002d ae06 SPLK #0FFFFh, IFR ;Clear any pending Ints
002e ffff
247 002f be40 EINT ;Enable global Ints
248 ;------------------------------------------------------------------------------------------
249 ;Hardware/Board Specific Initialization
250 ;------------------------------------------------------------------------------------------
251 ;-----------------------------------------------------------------------
252 ;Enables PWM signals on DMC1500
253 ;-----------------------------------------------------------------------
254 .if (x243|x2407) ;target dependancy
255 0030 POINT_PF2
1 0030 bce1 LDP #0E1h
256 0031 1010 LACC OCRA
257 0032 bfb0 AND #0BFFFh
0033 bfff
258 0034 9010 SACL OCRA ;Select Secondary function IOPB6
259
260 0035 101a LACC PBDATDIR
261 0036 bfc0 OR #04000h
0037 4000
262 0038 901a SACL PBDATDIR ;Set IOPB6 as output
263
264 0039 101a LACC PBDATDIR
265 003a bfb0 AND #0FFBFh ;Set IOPB6 low, Enable PWM
003b ffbf
266 ; OR #00040h ;Set IOPB6 high, Disable PWM
267 003c 901a SACL PBDATDIR
268 .endif
269
270 ;Selects ADC Channels
271
272 003d bc00! ldp #A4_ch_sel
273 .if (x2407)
274 ; SPLK #0cba5h, A4_ch_sel ;Chs 12,11,10,5 for 2407EVM with DMC1500
275 003e ae00! SPLK #06543h, A4_ch_sel ;Chs 6,5,4,3 for 2407eZdsp with DMC1500
003f 6543
276 .endif
277
278 .if (x243)
279 SPLK #06543h, A4_ch_sel ;Chs 6,5,4,3 for 243EVM with DMC1000
280 .endif
281
282
283 ;------------------------------------------------------------------------------------------
284 ;Motor Specific Parameters Initialization
285 ;------------------------------------------------------------------------------------------
286 ;Compressor motor 1
287 ;------------------------------------
TMS320C24xx COFF Assembler Version 7.02 Mon Apr 28 11:35:36 2003
Copyright (c) 1987-2002 Texas Instruments Incorporated
bldc3_21.asm PAGE 7
288 .if (cmp1)
289 ALIGN_DUTY .set 0F00h
290 LOOP_CNT_MAX .set 0
291
292 POINT_B0
293 ;For open loop speed ramp control
294 SPLK #0400h, cmtn_period_target ;Final commutation period
295 SPLK #500h, cmtn_period_setpt ;Initial commutation period
296
297 SPLK #0100, ramp_delay
298
299 ;For open loop D_func control
300 SPLK #0h, I_loop_flg ;start with open loop current
301 SPLK #ALIGN_DUTY, D_func_desired
302
303 .endif
304
305 ;Motor pac scientific
306 ;------------------------------------
307 .if (pxi)
308 ALIGN_DUTY .set 0F00h
309 LOOP_CNT_MAX .set 0
310
311 POINT_B0
312 ;For open loop speed ramp control
313 SPLK #0450h, cmtn_period_target ;Final commutation period
314 SPLK #500h, cmtn_period_setpt ;Initial commutation period
315
316 SPLK #050, ramp_delay
317
318 ;For open loop D_func control
319 SPLK #0h, I_loop_flg ;start with open loop current
320 SPLK #ALIGN_DUTY, D_func_desired
321
322 .endif
323
324 ;Motor asp
325 ;-----------------------------------
326 .if (asp)
327 3000 ALIGN_DUTY .set 03000h
328 0008 LOOP_CNT_MAX .set 8 ;
329 ;LOOP_CNT_MAX .set 2
330
331 0040 POINT_B0
1 0040 bc04 LDP #04h
332 ;For open loop speed ramp control
333 ; SPLK #0500h, cmtn_period_target ;Final ramp speed (lower val = higher speed)
334 ; SPLK #600h, cmtn_period_setpt ;Init ramp starting point
335 ; SPLK #050, ramp_delay ;For LF2407
336
337 0041 ae09- SPLK #0700h, cmtn_period_target ;Final ramp speed (lower val = higher speed)
0042 0700
338 0043 ae0a- SPLK #0C00h, cmtn_period_setpt ;Init ramp starting point
0044 0c00
TMS320C24xx COFF Assembler Version 7.02 Mon Apr 28 11:35:36 2003
Copyright (c) 1987-2002 Texas Instruments Incorporated
bldc3_21.asm PAGE 8
339 0045 ae0c- SPLK #0200, ramp_delay
0046 00c8
340
341 ;For open loop D_func control
342 0047 ae06- SPLK #0h, I_loop_flg ;start with open loop current
0048 0000
343 0049 ae07- SPLK #ALIGN_DUTY, D_func_desired ;set PWM duty cycle
004a 3000
344
345 .endif
346
347 ;Motor wjw
348 ;-----------------------------------
349 .if (wjw)
350 ALIGN_DUTY .set 01500h
351 LOOP_CNT_MAX .set 0
352
353 POINT_B0
354 ;For open loop speed ramp control
355 SPLK #0300h, cmtn_period_target ;Final ramp speed (lower val = higher speed)
356 SPLK #500h, cmtn_period_setpt ;Init ramp starting point
357 SPLK #0400, ramp_delay ;Set ramp rate (higher val = slower ramp)
358
359 ;For open loop D_func control
360 SPLK #0h, I_loop_flg ;start with open loop current
361 SPLK #ALIGN_DUTY, D_func_desired ;set PWM duty cycle
362
363 .endif
364
365 ;Motor kvb
366 ;-----------------------------
367 .if (kvb)
368 ALIGN_DUTY .set 0C00h
369 LOOP_CNT_MAX .set 1
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