📄 bldc.asm
字号:
.func 272
;>>>> void interrupt c_int03()
******************************************************
* FUNCTION DEF : _c_int03
******************************************************
_c_int03:
CALL I$$SAVE
SAR AR1,*
LARK AR0,1
LAR AR0,*0+
.line 3
;>>>> asm(" CLRC XF ");
CLRC XF
.line 5
;>>>> isr_ticker++;
;>>>> #if TARGET==F243
;>>>> EVIFRB=0x0ffff; /* Clear all Group A EV interrupt flags */
;>>>> #elif TARGET==F2407
LDPK _isr_ticker
LAC _isr_ticker
ADDK 1
SACL _isr_ticker
.line 12
;>>>> EVAIFRB=0x0ffff; /* Clear all EV1 Group A EV interrupt flags*/
;>>>> #endif/* #if TARGET */
LARK AR3,29744
MAR * ,AR3
SPLK #-1,*
.line 15
;>>>> if (bldc.align_flag != FALSE ) {
SSXM
LAC _bldc+7
BZ L2
.line 16
;>>>> bldc.mod6.cntr = 0;
LACK 0
SACL _bldc+13
.line 17
;>>>> pwm.cmtn_ptr_bd = 0;
SACL _pwm
.line 18
;>>>> pwm.update(&pwm);
LALK _pwm+0
MAR * ,AR1
SACL *+
LAC _pwm+5
CALA
MAR *-
.line 23
;>>>> if (bldc.cmtn.v_timer < V_TIMER_THRESHOLD){
SSXM
LDPK _bldc+33
LAC _bldc+33
SUBK 32512
BGEZ L3
.line 24
;>>>> update_v_timer();
CALL _update_v_timer
.line 25
;>>>> dac.update(&dac);
LALK _dac+0
SACL *+
LDPK _dac+5
LAC _dac+5
CALA
MAR *-
.line 26
;>>>> asm(" SETC XF ");
SETC XF
.line 27
;>>>> return;
B EPI0_2
L3:
.line 30
;>>>> bldc.align_flag = 0;
;>>>> #if (BUILDLEVEL==LEVEL1)
;>>>> BLDC_TI_Run(&bldc);
;>>>> pwm.cmtn_ptr_bd = bldc.mod6.cntr; /* Input to PWM driver */
;>>>> pwm.update(&pwm);
;>>>> #endif /* (BUILDLEVEL==LEVEL1) */
;>>>> #if (BUILDLEVEL==LEVEL2)
;>>>> bldc.cmtn.va = adc.c1_out;
;>>>> bldc.cmtn.vb = adc.c2_out;
;>>>> bldc.cmtn.vc = adc.c3_out;
;>>>> BLDC_TI_Run(&bldc);
;>>>> pwm.cmtn_ptr_bd = bldc.mod6.cntr; /* Input to PWM driver */
;>>>> pwm.update(&pwm);
;>>>> adc.update(&adc);
;>>>> #endif /* (BUILDLEVEL==LEVEL2) */
;>>>> #if (BUILDLEVEL==LEVEL3)
;>>>> bldc.cmtn.va = adc.c1_out;
;>>>> bldc.cmtn.vb = adc.c2_out;
;>>>> bldc.cmtn.vc = adc.c3_out;
;>>>> BLDC_TI_Run(&bldc);
;>>>> pwm.cmtn_ptr_bd = bldc.mod6.cntr; /* Input to PWM driver */
;>>>> pwm.update(&pwm);
;>>>> adc.update(&adc);
;>>>> #endif /* (BUILDLEVEL==LEVEL3) */
;>>>> #if (BUILDLEVEL==LEVEL4)
;>>>> bldc.cmtn.va = adc.c1_out;
;>>>> bldc.cmtn.vb = adc.c2_out;
;>>>> bldc.cmtn.vc = adc.c3_out;
;>>>> BLDC_TI_Run(&bldc);
;>>>> pwm.cmtn_ptr_bd = bldc.mod6.cntr; /* Input to PWM driver */
;>>>> pwm.d_func = bldc.rmp2.out;
;>>>> pwm.update(&pwm);
;>>>> adc.update(&adc);
;>>>> #endif /* (BUILDLEVEL==LEVEL4) */
;>>>> #if (BUILDLEVEL==LEVEL5)
LACK 0
SACL _bldc+7
L2:
.line 95
;>>>> bldc.cmtn.va = adc.c1_out;
BLKD #_adc+4,_bldc+23
.line 96
;>>>> bldc.cmtn.vb = adc.c2_out;
BLKD #_adc+5,_bldc+24
.line 97
;>>>> bldc.cmtn.vc = adc.c3_out;
BLKD #_adc+6,_bldc+25
.line 99
;>>>> bldc.pid2.fb_reg2 = adc.c4_out;
BLKD #_adc+7,_bldc+41
.line 101
;>>>> BLDC_TI_Run(&bldc);
LALK _bldc+0
MAR * ,AR1
SACL *+
CALL _BLDC_TI_Run
MAR *-
.line 103
;>>>> if(FALSE == bldc.I_loop_flg)
SSXM
LDPK _bldc+3
LAC _bldc+3
BNZ L4
.line 104
;>>>> pwm.d_func = bldc.rmp2.out;
;>>>> else
BLKD #_bldc+59,_pwm+3
B L5
L4:
.line 106
;>>>> pwm.d_func = bldc.pid2.out_reg2;
BLKD #_bldc+52,_pwm+3
L5:
.line 108
;>>>> pwm.cmtn_ptr_bd = bldc.mod6.cntr; /* Input to PWM driver */
BLKD #_bldc+13,_pwm
.line 109
;>>>> pwm.update(&pwm);
LALK _pwm+0
SACL *+
LAC _pwm+5
CALA
MAR *-
.line 110
;>>>> adc.update(&adc);
;>>>> #endif /* (BUILDLEVEL==LEVEL5) */
LALK _adc+0
SACL *+
LDPK _adc+10
LAC _adc+10
CALA
MAR *-
.line 114
;>>>> update_v_timer();
CALL _update_v_timer
.line 115
;>>>> dac.update(&dac);
LALK _dac+0
SACL *+
LDPK _dac+5
LAC _dac+5
CALA
MAR *-
.line 117
;>>>> asm(" SETC XF ");
SETC XF
EPI0_2:
.line 120
SBRK 1
B I$$REST,AR1 ;and return
.endfunc 391,000000000H,1
.sym _RstSystem,_RstSystem,32,2,0
.globl _RstSystem
.func 394
;>>>> void RstSystem(void)
;>>>> #if (TARGET==F243)
;>>>> disable_ints(); /* Make sure the interrupts are disabled */
;>>>> IMR = 0x00; /* Mask all interrupts */
;>>>> IFR = 0x00ff; /* Clear any pending interrupts, if any */
;>>>> PIRQR0 = PIRQR0 & 0x0fffe; /* Clear pending PDP flag */
;>>>> EVIFRA = EVIFRA | 0x0001; /* Clear PDP int flag */
;>>>> asm(" CLRC SXM "); /* Clear signextension mode */
;>>>> asm(" CLRC OVM "); /* Reset overflow mode */
;>>>> asm(" CLRC CNF "); /* Config block B0 to data memory */
;>>>> asm(" SPM 0 "); /* Set product mode at 0 */
;>>>> WSGR=WAIT_STATES; /* Initialize Wait State Generator */
;>>>> SCSR=0x40c0; /* Init SCSR */
;>>>> wdog.disable(); /* Vccp/Wddis pin/bit must be high */
;>>>> wdog.reset(); /* reset watchdog counter */
;>>>> EVIMRB=0x0004; /* Enable the timer2 underflow interrupt */
;>>>> EVIFRA = 0xFFFF; /* Clear all Group A interrupt flags */
;>>>> EVIFRB = 0xFFFF; /* Clear all Group B interrupt flags */
;>>>> EVIFRC = 0xFFFF; /* Clear all Group C interrupt flags */
;>>>> #if (REAL_TIME==TRUE)
;>>>> IMR = 0x0044; /* En Int lvl 3 & 7 (T2 ISR) */
;>>>> #endif /* (REAL_TIME==TRUE) */
;>>>> #if (REAL_TIME==FALSE)
;>>>> IMR = 0x0004; /* En Int lvl 3 (T2 ISR) */
;>>>> #endif /* (REAL_TIME==TRUE)*/
;>>>> #endif /* (TARGET==F243) */
;>>>> #if (TARGET==F2407)
******************************************************
* FUNCTION DEF : _RstSystem
******************************************************
_RstSystem:
POPD *+
SAR AR0,*+
SAR AR1,*
LARK AR0,1
LAR AR0,*0+
.line 42
;>>>> disable_ints(); /* Make sure the interrupts are disabled */
CALL _disable_ints
.line 43
;>>>> IMR = 0x00; /* Mask all interrupts */
LARK AR3,4
LACK 0
MAR * ,AR3
SACL *
.line 44
;>>>> IFR = 0x00ff; /* Clear any pending interrupts, if any */
LACK 255
ADRK 2
SACL * ,AR4
.line 45
;>>>> PIRQR0 = PIRQR0 & 0x0fffe; /* Clear pending PDP flag */
LARK AR4,28688
LACK 65534
AND *
SACL *
.line 46
;>>>> PIRQR2 = PIRQR2 & 0x0fffe; /* Clear pending PDP flag */
LACK 65534
ADRK 2
AND *
SACL * ,AR5
.line 48
;>>>> EVAIFRA = EVAIFRA | 0x0001; /* Clear PDPINTA flag */
LARK AR5,29743
LACK 1
OR *
SACL *
.line 49
;>>>> EVBIFRA = EVBIFRA | 0x0001; /* Clear PDPINTB flag */
LARK AR5,29999
LACK 1
OR *
SACL *
.line 51
;>>>> asm(" CLRC SXM "); /* Clear signextension mode */
CLRC SXM
.line 52
;>>>> asm(" CLRC OVM "); /* Reset overflow mode */
CLRC OVM
.line 53
;>>>> asm(" CLRC CNF "); /* Config block B0 to data memory */
CLRC CNF
.line 54
;>>>> asm(" SPM 0 "); /* Set product mode at 0 */
SPM 0
.line 56
;>>>> WSGR=WAIT_STATES; /* Initialize Wait State Generator */
MAR * ,AR3
ADRK 186
MAR * ,AR0
SAR AR3,*
OUT * ,0ffffh,AR3
.line 57
;>>>> SCSR1=0x0085; /* Init SCSR1 */
SBRK 59
MAR * ,AR4
ADRK 6
SAR AR3,* ,AR1
.line 58
;>>>> wdog.disable(); /* Vccp/Wddis pin/bit must be high */
LDPK _wdog
LAC _wdog
CALA
.line 59
;>>>> wdog.reset(); /* reset watchdog counter */
LDPK _wdog+1
LAC _wdog+1
CALA
.line 61
;>>>> EVAIMRB=0x0004; /* Enable the timer underflow interrupt */
LARK AR3,29741
LACK 4
MAR * ,AR3
SACL *
.line 63
;>>>> EVAIFRA = 0XFFFF; /* Clear all Group A interrupt flags */
ADRK 2
SPLK #-1,*+
.line 64
;>>>> EVAIFRB = 0XFFFF; /* Clear all Group B interrupt flags */
SPLK #-1,*+
.line 65
;>>>> EVAIFRC = 0XFFFF; /* Clear all Group C interrupt flags */
;>>>> #if (REAL_TIME==TRUE)
SPLK #-1,* ,AR4
.line 68
;>>>> IMR = 0X0044; /* En Int lvl 3 & 7 (T2 ISR) */
;>>>> #endif /* (REAL_TIME==TRUE) */
;>>>> #if (REAL_TIME==FALSE)
;>>>> IMR = 0X0004; /* En Int lvl 3 (T2 ISR) */
;>>>> #endif /* (REAL_TIME==TRUE)*/
;>>>> #endif /* (TARGET==F2407) */
LARK AR4,4
LACK 68
SACL * ,AR1
EPI0_3:
.line 77
SBRK 2
LAR AR0,*-
PSHD *
RET
.endfunc 470,000000000H,1
.sym _phantom,_phantom,32,2,0
.globl _phantom
.func 473
;>>>> void interrupt phantom(void)
;>>>> static int phantom_count;
******************************************************
* FUNCTION DEF : _phantom
******************************************************
_phantom:
CALL I$$SAVE
SAR AR1,*
LARK AR0,1
LAR AR0,*0+
.sym _phantom_count,_phantom_count$1,4,3,16
.line 5
;>>>> phantom_count ++;
LDPK _phantom_count$1
LAC _phantom_count$1
ADDK 1
SACL _phantom_count$1
EPI0_4:
.line 15
SBRK 1
B I$$REST,AR1 ;and return
.endfunc 487,000000000H,1
.sym _rtmon_init,_rtmon_init,32,2,0
.globl _rtmon_init
.func 493
;>>>> void rtmon_init(void)
******************************************************
* FUNCTION DEF : _rtmon_init
******************************************************
_rtmon_init:
POPD *+
SAR AR0,*+
SAR AR1,*
LARK AR0,1
LAR AR0,*0+
.line 3
;>>>> asm(" CALL MON_RT_CNFG ");
CALL MON_RT_CNFG
EPI0_5:
.line 4
SBRK 2
LAR AR0,*-
PSHD *
RET
.endfunc 496,000000000H,1
.sym _time_base_init,_time_base_init,32,2,0
.globl _time_base_init
.func 503
;>>>> void time_base_init(void)
******************************************************
* FUNCTION DEF : _time_base_init
******************************************************
_time_base_init:
POPD *+
SAR AR0,*+
SAR AR1,*
LARK AR0,1
LAR AR0,*0+,AR3
.line 3
;>>>> T2PR = SYSTEM_INT_PERIOD; /* Initialize period register */
LARK AR3,29703
SPLK #1000,*+
.line 10
;>>>> T2CON = 0x9040;
SPLK #-28608,* ,AR1
EPI0_6:
.line 12
SBRK 2
LAR AR0,*-
PSHD *
RET
.endfunc 514,000000000H,1
.sym _evm_pwm_init,_evm_pwm_init,32,2,0
.globl _evm_pwm_init
.func 516
;>>>> void evm_pwm_init(void)
******************************************************
* FUNCTION DEF : _evm_pwm_init
******************************************************
_evm_pwm_init:
POPD *+
SAR AR0,*+
SAR AR1,*
LARK AR0,1
LAR AR0,*0+,AR3
.line 3
;>>>> MCRA = MCRA & 0XBFFF; /* Select Secondary function IOPB6 */
LARK AR3,28816
LACK 49151
AND *
SACL *
.line 4
;>>>> PBDATDIR = PBDATDIR |0X4000; /* Set IOPB6 as output */
LACK 16384
ADRK 10
OR *
SACL *
.line 5
;>>>> PBDATDIR = PBDATDIR & EVM_IOPB6; /* Set IOPB6 low/high, Enable/disable PWM */
LACK 65471
AND *
SACL * ,AR1
EPI0_7:
.line 6
SBRK 2
LAR AR0,*-
PSHD *
RET
.endfunc 521,000000000H,1
.sym _update_v_timer,_update_v_timer,32,2,0
.globl _update_v_timer
.func 523
;>>>> void update_v_timer(void)
******************************************************
* FUNCTION DEF : _update_v_timer
******************************************************
_update_v_timer:
POPD *+
SAR AR0,*+
SAR AR1,*
LARK AR0,1
LAR AR0,*0+
.line 3
;>>>> bldc.cmtn.v_timer++; /* Inc virtual timer */
LDPK _bldc+33
LAC _bldc+33
ADDK 1
SACL _bldc+33
.line 4
;>>>> bldc.cmtn.v_timer = bldc.cmtn.v_timer & 0x7fff; /* Force 15 bit wrap around and save */
ANDK 32767
SACL _bldc+33
EPI0_8:
.line 5
SBRK 2
LAR AR0,*-
PSHD *
RET
.endfunc 527,000000000H,1
.sym _isr_ticker,_isr_ticker,4,2,16
.globl _isr_ticker
*****************************************************
* UNDEFINED REFERENCES *
*****************************************************
.global _enable_ints
.global I$$SAVE
.global I$$REST
.global _disable_ints
.end
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