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📄 bldc.lst

📁 直流无刷电机控制程序
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     812 00dc be30          CALA
     813                    .line   59
     814            ;>>>>           wdog.reset();             /* reset watchdog counter */
     815 00dd bc00-         LDPK    _wdog+1
     816 00de 1055-         LAC     _wdog+1
     817 00df be30          CALA
     818                    .line   61
     819            ;>>>>           EVAIMRB=0x0004;        /* Enable the timer underflow interrupt */
     820 00e0 bf0b          LARK    AR3,29741
         00e1 742d  
     821 00e2 b904          LACK    4
     822 00e3 8b8b          MAR     * ,AR3
     823 00e4 9080          SACL    * 
     824                    .line   63
     825            ;>>>>           EVAIFRA = 0XFFFF;      /* Clear all Group A interrupt flags */
     826 00e5 7802          ADRK    2
     827 00e6 aea0          SPLK    #-1,*+
         00e7 ffff  
     828                    .line   64
     829            ;>>>>           EVAIFRB = 0XFFFF;      /* Clear all Group B interrupt flags */
     830 00e8 aea0          SPLK    #-1,*+
         00e9 ffff  
     831                    .line   65
     832            ;>>>>           EVAIFRC = 0XFFFF;      /* Clear all Group C interrupt flags */
     833            ;>>>>           #if (REAL_TIME==TRUE)
     834 00ea ae8c          SPLK    #-1,* ,AR4
         00eb ffff  
     835                    .line   68
     836            ;>>>>           IMR = 0X0044;                /* En Int lvl 3 & 7 (T2 ISR) */
     837            ;>>>>           #endif /* (REAL_TIME==TRUE) */
     838            ;>>>>           #if (REAL_TIME==FALSE)
     839            ;>>>>           IMR = 0X0004;                /* En Int lvl 3   (T2 ISR) */
     840            ;>>>>           #endif /* (REAL_TIME==TRUE)*/
     841            ;>>>>   #endif /* (TARGET==F2407) */
TMS320C24xx COFF Assembler Version 7.04  Tue May 06 15:43:45 2008
Copyright (c) 1987-2003  Texas Instruments Incorporated 
../temp/bldc.asm                                                     PAGE   19

     842 00ec b404          LARK    AR4,4
     843 00ed b944          LACK    68
     844 00ee 9089          SACL    * ,AR1
     845 00ef       EPI0_3:
     846                    .line   77
     847 00ef 7c02          SBRK    2
     848 00f0 0090          LAR     AR0,*-
     849 00f1 7680          PSHD    *
     850 00f2 ef00          RET
     851            
     852                    .endfunc        470,000000000H,1
     853            
     854                    .sym    _phantom,_phantom,32,2,0
     855                    .globl  _phantom
     856            
     857                    .func   473
     858            ;>>>>   void interrupt phantom(void)
     859            ;>>>>     static int phantom_count;
     860            ******************************************************
     861            * FUNCTION DEF : _phantom
     862            ******************************************************
     863 00f3       _phantom:
     864 00f3 7a80          CALL    I$$SAVE
         00f4 0000! 
     865 00f5 8180          SAR     AR1,*
     866 00f6 b001          LARK    AR0,1
     867 00f7 00e0          LAR     AR0,*0+
     868            
     869            
     870                    .sym    _phantom_count,_phantom_count$1,4,3,16
     871                    .line   5
     872            ;>>>>     phantom_count ++;
     873 00f8 bc00-         LDPK    _phantom_count$1
     874 00f9 1056-         LAC     _phantom_count$1
     875 00fa b801          ADDK    1
     876 00fb 9056-         SACL    _phantom_count$1
     877 00fc       EPI0_4:
     878                    .line   15
     879 00fc 7c01          SBRK    1
     880 00fd 7989          B       I$$REST,AR1   ;and return
         00fe 0000! 
     881            
     882                    .endfunc        487,000000000H,1
     883            
     884                    .sym    _rtmon_init,_rtmon_init,32,2,0
     885                    .globl  _rtmon_init
     886            
     887                    .func   493
     888            ;>>>>   void rtmon_init(void)
     889            ******************************************************
     890            * FUNCTION DEF : _rtmon_init
     891            ******************************************************
     892 00ff       _rtmon_init:
     893 00ff 8aa0          POPD    *+
TMS320C24xx COFF Assembler Version 7.04  Tue May 06 15:43:45 2008
Copyright (c) 1987-2003  Texas Instruments Incorporated 
../temp/bldc.asm                                                     PAGE   20

     894 0100 80a0          SAR     AR0,*+
     895 0101 8180          SAR     AR1,*
     896 0102 b001          LARK    AR0,1
     897 0103 00e0          LAR     AR0,*0+
     898            
     899                    .line   3
     900            ;>>>>       asm("       CALL    MON_RT_CNFG ");
     901 0104 7a80         CALL    MON_RT_CNFG 
         0105 0000! 
     902 0106       EPI0_5:
     903                    .line   4
     904 0106 7c02          SBRK    2
     905 0107 0090          LAR     AR0,*-
     906 0108 7680          PSHD    *
     907 0109 ef00          RET
     908            
     909                    .endfunc        496,000000000H,1
     910            
     911                    .sym    _time_base_init,_time_base_init,32,2,0
     912                    .globl  _time_base_init
     913            
     914                    .func   503
     915            ;>>>>   void time_base_init(void)
     916            ******************************************************
     917            * FUNCTION DEF : _time_base_init
     918            ******************************************************
     919 010a       _time_base_init:
     920 010a 8aa0          POPD    *+
     921 010b 80a0          SAR     AR0,*+
     922 010c 8180          SAR     AR1,*
     923 010d b001          LARK    AR0,1
     924 010e 00eb          LAR     AR0,*0+,AR3
     925            
     926                    .line   3
     927            ;>>>>           T2PR = SYSTEM_INT_PERIOD;  /* Initialize period register */
     928 010f bf0b          LARK    AR3,29703
         0110 7407  
     929 0111 aea0          SPLK    #1000,*+
         0112 03e8  
     930                    .line   10
     931            ;>>>>           T2CON = 0x9040;
     932 0113 ae89          SPLK    #-28608,* ,AR1
         0114 9040  
     933 0115       EPI0_6:
     934                    .line   12
     935 0115 7c02          SBRK    2
     936 0116 0090          LAR     AR0,*-
     937 0117 7680          PSHD    *
     938 0118 ef00          RET
     939            
     940                    .endfunc        514,000000000H,1
     941            
     942                    .sym    _evm_pwm_init,_evm_pwm_init,32,2,0
     943                    .globl  _evm_pwm_init
TMS320C24xx COFF Assembler Version 7.04  Tue May 06 15:43:45 2008
Copyright (c) 1987-2003  Texas Instruments Incorporated 
../temp/bldc.asm                                                     PAGE   21

     944            
     945                    .func   516
     946            ;>>>>   void evm_pwm_init(void)
     947            ******************************************************
     948            * FUNCTION DEF : _evm_pwm_init
     949            ******************************************************
     950 0119       _evm_pwm_init:
     951 0119 8aa0          POPD    *+
     952 011a 80a0          SAR     AR0,*+
     953 011b 8180          SAR     AR1,*
     954 011c b001          LARK    AR0,1
     955 011d 00eb          LAR     AR0,*0+,AR3
     956            
     957                    .line   3
     958            ;>>>>           MCRA     = MCRA & 0XBFFF;        /* Select Secondary function IOPB6 */
     959 011e bf0b          LARK    AR3,28816
         011f 7090  
     960 0120 bf80          LACK    49151
         0121 bfff  
     961 0122 6e80          AND     * 
     962 0123 9080          SACL    * 
     963                    .line   4
     964            ;>>>>           PBDATDIR = PBDATDIR |0X4000;     /* Set IOPB6 as output        */
     965 0124 bf80          LACK    16384
         0125 4000  
     966 0126 780a          ADRK    10
     967 0127 6d80          OR      * 
     968 0128 9080          SACL    * 
     969                    .line   5
     970            ;>>>>           PBDATDIR = PBDATDIR & EVM_IOPB6; /* Set IOPB6 low/high, Enable/disable PWM  */
     971 0129 bf80          LACK    65471
         012a ffbf  
     972 012b 6e80          AND     * 
     973 012c 9089          SACL    * ,AR1
     974 012d       EPI0_7:
     975                    .line   6
     976 012d 7c02          SBRK    2
     977 012e 0090          LAR     AR0,*-
     978 012f 7680          PSHD    *
     979 0130 ef00          RET
     980            
     981                    .endfunc        521,000000000H,1
     982            
     983                    .sym    _update_v_timer,_update_v_timer,32,2,0
     984                    .globl  _update_v_timer
     985            
     986                    .func   523
     987            ;>>>>   void update_v_timer(void)
     988            ******************************************************
     989            * FUNCTION DEF : _update_v_timer
     990            ******************************************************
     991 0131       _update_v_timer:
     992 0131 8aa0          POPD    *+
     993 0132 80a0          SAR     AR0,*+
TMS320C24xx COFF Assembler Version 7.04  Tue May 06 15:43:45 2008
Copyright (c) 1987-2003  Texas Instruments Incorporated 
../temp/bldc.asm                                                     PAGE   22

     994 0133 8180          SAR     AR1,*
     995 0134 b001          LARK    AR0,1
     996 0135 00e0          LAR     AR0,*0+
     997            
     998                    .line   3
     999            ;>>>>      bldc.cmtn.v_timer++;                  /* Inc virtual timer */
    1000 0136 bc00-         LDPK    _bldc+33
    1001 0137 1038-         LAC     _bldc+33
    1002 0138 b801          ADDK    1
    1003 0139 9038-         SACL    _bldc+33
    1004                    .line   4
    1005            ;>>>>      bldc.cmtn.v_timer = bldc.cmtn.v_timer & 0x7fff;   /* Force 15 bit wrap around and save */
    1006 013a bfb0          ANDK    32767
         013b 7fff  
    1007 013c 9038-         SACL    _bldc+33
    1008 013d       EPI0_8:
    1009                    .line   5
    1010 013d 7c02          SBRK    2
    1011 013e 0090          LAR     AR0,*-
    1012 013f 7680          PSHD    *
    1013 0140 ef00          RET
    1014            
    1015                    .endfunc        527,000000000H,1
    1016            
    1017                    .sym    _isr_ticker,_isr_ticker,4,2,16
    1018                    .globl  _isr_ticker
    1019            *****************************************************
    1020            * UNDEFINED REFERENCES                              *
    1021            *****************************************************
    1022                    .global _enable_ints
    1023                    .global I$$SAVE
    1024                    .global I$$REST
    1025                    .global _disable_ints
    1026                    .end

 No Errors,  No Warnings

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