📄 bldc.lst
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599 ;>>>> bldc.cmtn.vb = adc.c2_out;
600 ;>>>> bldc.cmtn.vc = adc.c3_out;
601 ;>>>> BLDC_TI_Run(&bldc);
602 ;>>>> pwm.cmtn_ptr_bd = bldc.mod6.cntr; /* Input to PWM driver */
603 ;>>>> pwm.update(&pwm);
604 ;>>>> adc.update(&adc);
605 ;>>>> #endif /* (BUILDLEVEL==LEVEL2) */
606 ;>>>> #if (BUILDLEVEL==LEVEL3)
607 ;>>>> bldc.cmtn.va = adc.c1_out;
608 ;>>>> bldc.cmtn.vb = adc.c2_out;
609 ;>>>> bldc.cmtn.vc = adc.c3_out;
610 ;>>>> BLDC_TI_Run(&bldc);
611 ;>>>> pwm.cmtn_ptr_bd = bldc.mod6.cntr; /* Input to PWM driver */
612 ;>>>> pwm.update(&pwm);
613 ;>>>> adc.update(&adc);
614 ;>>>> #endif /* (BUILDLEVEL==LEVEL3) */
615 ;>>>> #if (BUILDLEVEL==LEVEL4)
616 ;>>>> bldc.cmtn.va = adc.c1_out;
617 ;>>>> bldc.cmtn.vb = adc.c2_out;
618 ;>>>> bldc.cmtn.vc = adc.c3_out;
619 ;>>>> BLDC_TI_Run(&bldc);
620 ;>>>> pwm.cmtn_ptr_bd = bldc.mod6.cntr; /* Input to PWM driver */
621 ;>>>> pwm.d_func = bldc.rmp2.out;
622 ;>>>> pwm.update(&pwm);
623 ;>>>> adc.update(&adc);
624 ;>>>> #endif /* (BUILDLEVEL==LEVEL4) */
625 ;>>>> #if (BUILDLEVEL==LEVEL5)
626 0071 b900 LACK 0
627 0072 901e- SACL _bldc+7
628 0073 L2:
629 .line 95
630 ;>>>> bldc.cmtn.va = adc.c1_out;
631 0073 a82e- BLKD #_adc+4,_bldc+23
0074 0010-
632 .line 96
633 ;>>>> bldc.cmtn.vb = adc.c2_out;
634 0075 a82f- BLKD #_adc+5,_bldc+24
0076 0011-
635 .line 97
636 ;>>>> bldc.cmtn.vc = adc.c3_out;
637 0077 a830- BLKD #_adc+6,_bldc+25
0078 0012-
638 .line 99
639 ;>>>> bldc.pid2.fb_reg2 = adc.c4_out;
640 0079 a840- BLKD #_adc+7,_bldc+41
007a 0013-
641 .line 101
642 ;>>>> BLDC_TI_Run(&bldc);
643 007b bf80 LALK _bldc+0
007c 0017-
644 007d 8b89 MAR * ,AR1
645 007e 90a0 SACL *+
646 007f 7a80 CALL _BLDC_TI_Run
0080 0000!
TMS320C24xx COFF Assembler Version 7.04 Tue May 06 15:43:45 2008
Copyright (c) 1987-2003 Texas Instruments Incorporated
../temp/bldc.asm PAGE 15
647 0081 8b90 MAR *-
648 .line 103
649 ;>>>> if(FALSE == bldc.I_loop_flg)
650 0082 be47 SSXM
651 0083 bc00- LDPK _bldc+3
652 0084 101a- LAC _bldc+3
653 0085 e308 BNZ L4
0086 008b'
654 .line 104
655 ;>>>> pwm.d_func = bldc.rmp2.out;
656 ;>>>> else
657 0087 a809- BLKD #_bldc+59,_pwm+3
0088 0052-
658 0089 7980 B L5
008a 008d'
659 008b L4:
660 .line 106
661 ;>>>> pwm.d_func = bldc.pid2.out_reg2;
662 008b a809- BLKD #_bldc+52,_pwm+3
008c 004b-
663 008d L5:
664 .line 108
665 ;>>>> pwm.cmtn_ptr_bd = bldc.mod6.cntr; /* Input to PWM driver */
666 008d a806- BLKD #_bldc+13,_pwm
008e 0024-
667 .line 109
668 ;>>>> pwm.update(&pwm);
669 008f bf80 LALK _pwm+0
0090 0006-
670 0091 90a0 SACL *+
671 0092 100b- LAC _pwm+5
672 0093 be30 CALA
673 0094 8b90 MAR *-
674 .line 110
675 ;>>>> adc.update(&adc);
676 ;>>>> #endif /* (BUILDLEVEL==LEVEL5) */
677 0095 bf80 LALK _adc+0
0096 000c-
678 0097 90a0 SACL *+
679 0098 bc00- LDPK _adc+10
680 0099 1016- LAC _adc+10
681 009a be30 CALA
682 009b 8b90 MAR *-
683 .line 114
684 ;>>>> update_v_timer();
685 009c 7a80 CALL _update_v_timer
009d 0131'
686 .line 115
687 ;>>>> dac.update(&dac);
688 009e bf80 LALK _dac+0
009f 0000-
689 00a0 90a0 SACL *+
690 00a1 bc00- LDPK _dac+5
691 00a2 1005- LAC _dac+5
TMS320C24xx COFF Assembler Version 7.04 Tue May 06 15:43:45 2008
Copyright (c) 1987-2003 Texas Instruments Incorporated
../temp/bldc.asm PAGE 16
692 00a3 be30 CALA
693 00a4 8b90 MAR *-
694 .line 117
695 ;>>>> asm(" SETC XF ");
696 00a5 be4d SETC XF
697 00a6 EPI0_2:
698 .line 120
699 00a6 7c01 SBRK 1
700 00a7 7989 B I$$REST,AR1 ;and return
00a8 0000!
701
702 .endfunc 391,000000000H,1
703
704 .sym _RstSystem,_RstSystem,32,2,0
705 .globl _RstSystem
706
707 .func 394
708 ;>>>> void RstSystem(void)
709 ;>>>> #if (TARGET==F243)
710 ;>>>> disable_ints(); /* Make sure the interrupts are disabled */
711 ;>>>> IMR = 0x00; /* Mask all interrupts */
712 ;>>>> IFR = 0x00ff; /* Clear any pending interrupts, if any */
713 ;>>>> PIRQR0 = PIRQR0 & 0x0fffe; /* Clear pending PDP flag */
714 ;>>>> EVIFRA = EVIFRA | 0x0001; /* Clear PDP int flag */
715 ;>>>> asm(" CLRC SXM "); /* Clear signextension mode */
716 ;>>>> asm(" CLRC OVM "); /* Reset overflow mode */
717 ;>>>> asm(" CLRC CNF "); /* Config block B0 to data memory */
718 ;>>>> asm(" SPM 0 "); /* Set product mode at 0 */
719 ;>>>> WSGR=WAIT_STATES; /* Initialize Wait State Generator */
720 ;>>>> SCSR=0x40c0; /* Init SCSR */
721 ;>>>> wdog.disable(); /* Vccp/Wddis pin/bit must be high */
722 ;>>>> wdog.reset(); /* reset watchdog counter */
723 ;>>>> EVIMRB=0x0004; /* Enable the timer2 underflow interrupt */
724 ;>>>> EVIFRA = 0xFFFF; /* Clear all Group A interrupt flags */
725 ;>>>> EVIFRB = 0xFFFF; /* Clear all Group B interrupt flags */
726 ;>>>> EVIFRC = 0xFFFF; /* Clear all Group C interrupt flags */
727 ;>>>> #if (REAL_TIME==TRUE)
728 ;>>>> IMR = 0x0044; /* En Int lvl 3 & 7 (T2 ISR) */
729 ;>>>> #endif /* (REAL_TIME==TRUE) */
730 ;>>>> #if (REAL_TIME==FALSE)
731 ;>>>> IMR = 0x0004; /* En Int lvl 3 (T2 ISR) */
732 ;>>>> #endif /* (REAL_TIME==TRUE)*/
733 ;>>>> #endif /* (TARGET==F243) */
734 ;>>>> #if (TARGET==F2407)
735 ******************************************************
736 * FUNCTION DEF : _RstSystem
737 ******************************************************
738 00a9 _RstSystem:
739 00a9 8aa0 POPD *+
740 00aa 80a0 SAR AR0,*+
741 00ab 8180 SAR AR1,*
742 00ac b001 LARK AR0,1
743 00ad 00e0 LAR AR0,*0+
744
TMS320C24xx COFF Assembler Version 7.04 Tue May 06 15:43:45 2008
Copyright (c) 1987-2003 Texas Instruments Incorporated
../temp/bldc.asm PAGE 17
745 .line 42
746 ;>>>> disable_ints(); /* Make sure the interrupts are disabled */
747 00ae 7a80 CALL _disable_ints
00af 0000!
748 .line 43
749 ;>>>> IMR = 0x00; /* Mask all interrupts */
750 00b0 b304 LARK AR3,4
751 00b1 b900 LACK 0
752 00b2 8b8b MAR * ,AR3
753 00b3 9080 SACL *
754 .line 44
755 ;>>>> IFR = 0x00ff; /* Clear any pending interrupts, if any */
756 00b4 b9ff LACK 255
757 00b5 7802 ADRK 2
758 00b6 908c SACL * ,AR4
759 .line 45
760 ;>>>> PIRQR0 = PIRQR0 & 0x0fffe; /* Clear pending PDP flag */
761 00b7 bf0c LARK AR4,28688
00b8 7010
762 00b9 bf80 LACK 65534
00ba fffe
763 00bb 6e80 AND *
764 00bc 9080 SACL *
765 .line 46
766 ;>>>> PIRQR2 = PIRQR2 & 0x0fffe; /* Clear pending PDP flag */
767 00bd bf80 LACK 65534
00be fffe
768 00bf 7802 ADRK 2
769 00c0 6e80 AND *
770 00c1 908d SACL * ,AR5
771 .line 48
772 ;>>>> EVAIFRA = EVAIFRA | 0x0001; /* Clear PDPINTA flag */
773 00c2 bf0d LARK AR5,29743
00c3 742f
774 00c4 b901 LACK 1
775 00c5 6d80 OR *
776 00c6 9080 SACL *
777 .line 49
778 ;>>>> EVBIFRA = EVBIFRA | 0x0001; /* Clear PDPINTB flag */
779 00c7 bf0d LARK AR5,29999
00c8 752f
780 00c9 b901 LACK 1
781 00ca 6d80 OR *
782 00cb 9080 SACL *
783 .line 51
784 ;>>>> asm(" CLRC SXM "); /* Clear signextension mode */
785 00cc be46 CLRC SXM
786 .line 52
787 ;>>>> asm(" CLRC OVM "); /* Reset overflow mode */
788 00cd be42 CLRC OVM
789 .line 53
790 ;>>>> asm(" CLRC CNF "); /* Config block B0 to data memory */
791 00ce be44 CLRC CNF
792 .line 54
TMS320C24xx COFF Assembler Version 7.04 Tue May 06 15:43:45 2008
Copyright (c) 1987-2003 Texas Instruments Incorporated
../temp/bldc.asm PAGE 18
793 ;>>>> asm(" SPM 0 "); /* Set product mode at 0 */
794 00cf bf00 SPM 0
795 .line 56
796 ;>>>> WSGR=WAIT_STATES; /* Initialize Wait State Generator */
797 00d0 8b8b MAR * ,AR3
798 00d1 78ba ADRK 186
799 00d2 8b88 MAR * ,AR0
800 00d3 8380 SAR AR3,*
801 00d4 0c8b OUT * ,0ffffh,AR3
00d5 ffff
802 .line 57
803 ;>>>> SCSR1=0x0085; /* Init SCSR1 */
804 00d6 7c3b SBRK 59
805 00d7 8b8c MAR * ,AR4
806 00d8 7806 ADRK 6
807 00d9 8389 SAR AR3,* ,AR1
808 .line 58
809 ;>>>> wdog.disable(); /* Vccp/Wddis pin/bit must be high */
810 00da bc00- LDPK _wdog
811 00db 1054- LAC _wdog
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