tsf_main.c

变频器程序

                       
void led(void)/*	interrupt void timer1_isr(void)*/
	{   
			led_cnt++;
     	if(led_cnt==1000)
     	{ 

     		/*----FOR DEMO BORAD-------*/
     		/**PBDATDIR = *PBDATDIR ^ 0x0001;*/    /*IOPB0*/ 
  		    *PFDATDIR = *PFDATDIR ^ 0x0040;    //IOPF6取反,使LED变化
     		
      
     
     		/*---counter reset---*/
     	led_cnt=0; 
     
     	
     } 
		
	}
	
	
	


      
 void observe(unsigned int x0,unsigned int x1,unsigned int x2,unsigned int x3)
 /*DA0~DA3 and DACUD must be defined as global variables*/
 { DAC0=x0;
   DAC1=x1;
   DAC2=x2;
   DAC3=x3;
   DAOUT=3;/*start DAC*/
 }


 
 void delay(void)       
 { int i;
   for(i=1;i<5000;i++)
   { asm(" NOP");
   }
 }
 
 void sysinit(void)
 {*IMR = 0x0000;
 
 /*** Configure the System Control and Status registers ***/
    *SCSR1 = 0x00FD;
/*
 bit 15        0:      reserved
 bit 14        0:      CLKOUT = CPUCLK
 bit 13-12     00:     IDLE1 selected for low-power mode
 bit 11-9      000:    PLL x4 mode
 bit 8         0:      reserved
 bit 7         1:      1 = enable ADC module clock
 bit 6         1:      1 = enable SCI module clock
 bit 5         1:      1 = enable SPI module clock
 bit 4         1:      1 = enable CAN module clock
 bit 3         1:      1 = enable EVB module clock
 bit 2         1:      1 = enable EVA module clock
 bit 1         0:      reserved
 bit 0         1:      clear the ILLADR bit           */

    *SCSR2 = (*SCSR2 | 0x000B) & 0x000F;
/*
 bit 15-6      0's:    reserved
 bit 5         0:      do NOT clear the WD OVERRIDE bit
 bit 4         0:      XMIF_HI-Z, 0=normal mode, 1=Hi-Z'd
 bit 3         1:      disable the boot ROM, enable the FLASH
 bit 2     no change   MP/MC* bit reflects state of MP/MC* pin
 bit 1-0      11:      11 = SARAM mapped to prog and data       */


/*** Disable the watchdog timer ***/
    *WDCR  = 0x00E8;
/*
 bits 15-8     0's:     reserved
 bit 7         1:       clear WD flag
 bit 6         1:       disable the dog
 bit 5-3       101:     must be written as 101
 bit 2-0       000:     WDCLK divider = 1          */


/*** Setup external memory interface for LF2407 EVM ***/
    WSGR = 0x0000;
    asm(" NOP");
    WSGR = 0x0040;   
    WSGR=0x0100;
/*
 bit 15-11     0's:    reserved
 bit 10-9      00:     bus visibility off
 bit 8-6       001:    1 wait-state for I/O space
 bit 5-3       000:    0 wait-state for data space
 bit 2-0       000:    0 wait state for program space   */


/*** Setup shared I/O pins ***/
   // *MCRA = 0x0FC0;                   /* group A pins */
   *MCRA = 0x0540;   
  // *MCRA = 0x0000; 
   
/* 0 0 0 0,1 1 1 1,1 1 0 0,0 0 0 0
   F E D C B A 9 8 7 6 5 4 3 2 1 0
 bit 15        0:      0=IOPB7,     1=TCLKINA
 bit 14        0:      0=IOPB6,     1=TDIRA
 bit 13        0:      0=IOPB5,     1=T2PWM/T2CMP
 bit 12        0:      0=IOPB4,     1=T1PWM/T1CMP
 bit 11        0:      0=IOPB3,     1=PWM6
 bit 10        0:      0=IOPB2,     1=PWM5
 bit 9         0:      0=IOPB1,     1=PWM4
 bit 8         0:      0=IOPB0,     1=PWM3
 bit 7         0:      0=IOPA7,     1=PWM2
 bit 6         0:      0=IOPA6,     1=PWM1
 bit 5         0:      0=IOPA5,     1=CAP3
 bit 4         0:      0=IOPA4,     1=CAP2/QEP2
 bit 3         0:      0=IOPA3,     1=CAP1/QEP1
 bit 2         0:      0=IOPA2,     1=XINT1
 bit 1         0:      0=IOPA1,     1=SCIRXD
 bit 0         0:      0=IOPA0,     1=SCITXD       */

    *MCRB = 0xFE00;                     /* group B pins */
/*
 bit 15        1:      0=reserved,  1=TMS2 (always write as 1)
 bit 14        1:      0=reserved,  1=TMS  (always write as 1)
 bit 13        1:      0=reserved,  1=TD0  (always write as 1)
 bit 12        1:      0=reserved,  1=TDI  (always write as 1)
 bit 11        1:      0=reserved,  1=TCK  (always write as 1)
 bit 10        1:      0=reserved,  1=EMU1 (always write as 1)
 bit 9         1:      0=reserved,  1=EMU0 (always write as 1)
 bit 8         0:      0=IOPD0,     1=XINT2/ADCSOC
 bit 7         0:      0=IOPC7,     1=CANRX
 bit 6         0:      0=IOPC6,     1=CANTX
 bit 5         0:      0=IOPC5,     1=SPISTE
 bit 4         0:      0=IOPC4,     1=SPICLK
 bit 3         0:      0=IOPC3,     1=SPISOMI
 bit 2         0:      0=IOPC2,     1=SPISIMO
 bit 1         0:      0=IOPC1,     1=BIO*
 bit 0         0:      0=IOPC0,     1=W/R*            */

    *MCRC = 0x0000;                     /* group C pins */
/*
 bit 15        0:      reserved
 bit 14        0:      0=IOPF6,     1=IOPF6
 bit 13        0:      0=IOPF5,     1=TCLKINB
 bit 12        0:      0=IOPF4,     1=TDIRB
 bit 11        0:      0=IOPF3,     1=T4PWM/T4CMP
 bit 10        0:      0=IOPF2,     1=T3PWM/T3CMP
 bit 9         0:      0=IOPF1,     1=CAP6
 bit 8         0:      0=IOPF0,     1=CAP5/QEP4
 bit 7         0:      0=IOPE7,     1=CAP4/QEP3
 bit 6         0:      0=IOPE6,     1=PWM12
 bit 5         0:      0=IOPE5,     1=PWM11
 bit 4         0:      0=IOPE4,     1=PWM10
 bit 3         0:      0=IOPE3,     1=PWM9
 bit 2         0:      0=IOPE2,     1=PWM8
 bit 1         0:      0=IOPE1,     1=PWM7
 bit 0         0:      0=IOPE0,     1=CLKOUT      */


/*** Configure IOPC0 pin as an output ***/
   /* *PCDATDIR = *PCDATDIR | 0x0100;   */
    

/*** Setup timers 1 and 2, and the PWM configuration ***/
*T1CON = 0x0000;                   /* disable timer 1 */
*T2CON = 0x0000;                   /* disable timer 2 */

*GPTCONA = 0x0080;                  /* configure GPTCONA */  //timer 1 下溢启动AD
/*     
 bit 15        0:      reserved
 bit 14        1:      software reset then set back to 0 
 bit 13        0:      T1STAT, read-only
 bit 12-11     00:     reserved
 bit 10-9      00:     T2TOADC, 00 = no timer2 event starts ADC
 bit 8-7       01:     T1TOADC, 00 = no timer1 event starts ADC
 bit 6         0:      TCOMPOE, 0 = Hi-z all timer compare outputs
 bit 5-4       00:     reserved
 bit 3-2       00:     T2PIN, 00 = forced low
 bit 1-0       00:     T1PIN, 00 = forced low  */     
 
 

 


   /* Timer 1: configure to clock the PWM on PWM1 pin */
   /* Symmetric PWM, 20KHz carrier frequency, 25% duty cycle */
*T1CNT = 0x0000;                     /* clear timer counter */
*T1PR = timer1_per;                /* set timer period 750*/// 4000
//*DBTCONA = 0x0FE4;                /* deadband units off */
    /*  0 0 0 0,1 1 1 1,1 1 1 0,0 0 0 0
      0 | | | | | | | | | | | | | | | RESERVED 
      1 | | | | | | | | | | | | | | RESERVED
      2 | | | | | | | | | | | | | -----|DBTPS0, 000 X/1;001 X/2; 010 X/4;
      3 | | | | | | | | | | | | -------|DBTPS1  011 X/8;100 X/16;101 X/32;  
      4 | | | | | | | | | | | ---------|DBTPS2  110 X/8;111 X/16;
      5 | | | | | | | | | | EDBT1, En bit of PWM1,PWM2
      6 | | | | | | | | | EDBT2, En bit of PWM3,PWM4
      7 | | | | | | | | EDBT3, En bit of PWM5,PWM6
      8 | | | | | | | --|DBT0  
      9 | | | | | | ----|DBT1
      A | | | | | ------|DBT2
      B | | | | --------|DBT3
      C | | | reserved
      D | | reserved
      E | reserved
      F reserved
*/
*CMPR1 = 0;/*pwm_duty;*/                 /* set PWM1 duty cycle 563*/
*CMPR2 = 0;/*pwm_duty;*/
*CMPR3 = 0;/*pwm_duty;*/ 
//*ACTRA =0xA888;                   /* PWM1 pin set active high */     
//*ACTRA=0x0666;
 *ACTRA=0xA555;
//*ACTRA=0x0000;
//*ACTRA=0x0FFF;
/*  1 0 1 0,1 0 1 0,1 0 1 0,0 0 1 0
    F E D C B A 9 8 7 6 5 4 3 2 1 0
 bit 15        0:      space vector dir is CCW (don't care)
 bit 14-12     000:    basic space vector is 000 (dont' care)
 bit 11-10     00:     PWM6/IOPB3 pin forced low
 bit 9-8       00:     PWM5/IOPB2 pin forced low
 bit 7-6       00:     PWM4/IOPB1 pin forced low
 bit 5-4       00:     PWM3/IOPB0 pin forced low
 bit 3-2       00:     PWM2/IOPA7 pin forced low
 bit 1-0       10:     PWM1/IOPA6 pin active high     */

*COMCONA = 0x8200;  /* configure COMCON register */
    /*  1 0 0 0,0 0 1 0,0 0 0 0,1 1 0 0
      0 | | | | | | | | | | | | | | | reserved, 
      1 | | | | | | | | | | | | | | reserved,
      2 | | | | | | | | | | | | | reserved, 
      3 | | | | | | | | | | | | reserved,
      4 | | | | | | | | | | | reserved,
      5 | | | | | | | | | | reserved,
      6 | | | | | | | | | reserved,
      7 | | | | | | | | reserved,
      8 | | | | | | | --PDPINTA STATUS  
      9 | | | | | | ----FCOMPOE; ENABLE
      A | | | | | --ACTRLD0
      B | | | | ----ACTRLD1
      C | | | ----SVENABLE
      D | | --CLD0| 00 when T1CNT=0(underflow); 01 when T1CNT=0 OR T1PR
      E | ----CLD1| 10 initiate    ; 11 reserved
      F CENABLE
     */ 


*T1CON = 0x0840;                   /* configure T1CON register */
    /*  0 0 0 0,1 0 0 0,0 1 0 0,0 0 0 0
      0 | | | | | | | | | | | | | | | SELT1PR/SELT3PR+ SELT1PR, 0 = use own period register 
      1 | | | | | | | | | | | | | | TECMP EN
      2 | | | | | | | | | | | | | TCLD0;period reload |00 for TxCNT=0; 01 for TxCNT=0/TxPER; 
      3 | | | | | | | | | | | | TCLD1;----------------|10 imidiately ; 11 reserved
      4 | | | | | | | | | | | TCLKS0-|00 internal cup clk; 01 external clock
      5 | | | | | | | | | | TCLKS1---|10 reserved        ; 11 QEP only for T2 and T4
      6 | | | | | | | | | TENABLE 
      7 | | | | | | | | T2SWT1/T4SWT1+
      8 | | | | | | | --TPS0|000 X/1  001 X/2  010 X/4  
      9 | | | | | | ----TPS1|011 X/8  100 X/16 101 X/32
      A | | | | | ------TPS2|110 X/64 111 X/128
      B | | | | --|TMODE0---|00-stop/hold 01-continuous inc & dec
      C | | | ----|TMODE1---|10-continuous inc 11-directional inc & dec
      D | | RESERVED
      E | SOFT
      F FREE
     */ 
/*     
 bit 15-14     00:     stop immediately on emulator suspend
 bit 13        0:      reserved
 bit 12-11     01:     01 = continous-up/down count mode
 bit 10-8      000:    000 = x/1 prescaler
 bit 7         0:      reserved in T1CON
 bit 6         1:      TENABLE, 1 = enable timer
 bit 5-4       00:     00 = CPUCLK is clock source
 bit 3-2       00:     
 bit 1         0:      
 bit 0         0:                  */

  
/* Timer 2: configure to generate a 250ms periodic interrupt */    
    *T2CNT = 0x0000;                    /* clear timer counter */
    //*T2PR = timer2_per;                 /* set timer period */
    //*T2CON = 0x124C;                    /* configure T2CON register */
/*     
 bit 15-14     00:     stop immediately on emulator suspend
 bit 13        0:      reserved
 bit 12-11     10:     10 = continous-up count mode
 bit 10-8      010:    111 = x/4 prescaler
 bit 7         0:      T2SWT1, 0 = use own TENABLE bit
 bit 6         0:      TENABLE, 0 =Disable timer operation
 bit 5-4       00:     00 = CPUCLK is clock source
 bit 3-2       00:     00 = reload compare reg on underflow
 bit 1         0:      0 = disable timer compare
 bit 0         0:      SELT1PR, 0 = use own period register     */

    

/*** Setup the core interrupts ***/
   // *IMR = 0x0000;                      /* clear the IMR register */
    /**IFR = 0x003F;*/                      /* clear any pending core interrupts */
    *IFR = 0xFFFF;
*IMR = 0x0002;                      /* enable desired core interruptsINT2 */
    /* 0 0 0 0 0 0 1 0
       | | | | | | | int1
       | | | | | | int2 
       | | | | | int3
       | | | | int4
       | | | int5
       | | int6
       | reserved
       reserved
    */
    
/*** Setup the event manager interrupts ***/
    *EVAIFRA = 0xFFFF;                  /* clear all EVA group A interrupts */   
    /*  0 0 0 0,0 0 0 0,1 0 0 0,0 0 0 0
      0 | | | | | | | | | | | | | | | PDPINTA FLAG;READ: 0 RESET;1 SET
      1 | | | | | | | | | | | | | | CMP1INT FLAG  ;WRITE:0 NO FUNCTION;1 RESET
      2 | | | | | | | | | | | | | CMP2INT FLAG
      3 | | | | | | | | | | | | COMP3INT FLAG
      4 | | | | | | | | | | | RESERVED
      5 | | | | | | | | | | RESERVED 
      6 | | | | | | | | | RESERVED 
      7 | | | | | | | | T1PINT FLAG 
      8 | | | | | | | T1CINT FLAG
      9 | | | | | | T1UFINT FLAG
      A | | | | | T1OFINT FLAG
      B | | | | RESERVED
      C | | | RESERVED
      D | | RESERVED
      E | RESERVED
      F RESERVED
     */ 
    *EVAIFRB = 0xFFFF;                  /* clear all EVA group B interrupts */
    /*  0 0 0 0,0 0 0 0,1 0 0 0,0 0 0 0
      0 | | | | | | | | | | | | | | | T2PINT FLAG
      1 | | | | | | | | | | | | | | T2CINT FLAG
      2 | | | | | | | | | | | | | T2UFINT FLAG
      3 | | | | | | | | | | | | T2OFINT FLAG
      4 | | | | | | | | | | | RESERVED
      5 | | | | | | | | | | RESERVED 
      6 | | | | | | | | | RESERVED 
      7 | | | | | | | | RESERVED 
      8 | | | | | | | RESERVED
      9 | | | | | | RESERVED
      A | | | | | RESERVED
      B | | | | RESERVED
      C | | | RESERVED
      D | | RESERVED
      E | RESERVED
      F RESERVED
     */ 
    *EVAIFRC = 0xFFFF;                  /* clear all EVA group C interrupts */
*EVAIMRA = 0x0200;                  /* enable desired EVA group A interrupts */
    /* 0 0 0 0,0 0 1 0,0 0 0 0,0 0 0 0
       | | | | | | | | | | | | | | | PDPINTA EN
       | | | | | | | | | | | | | | CMP1INT EN
       | | | | | | | | | | | | | CMP2INT EN
       | | | | | | | | | | | | COMP3INT EN
       | | | | | | | | | | | RESERVED
       | | | | | | | | | | RESERVED 
       | | | | | | | | | RESERVED 
       | | | | | | | | T1PINT EN 
       | | | | | | | T1CINT EN
       | | | | | | T1UFINT EN
       | | | | | T1OFINT EN
        RESERVED
     */ 
     
*EVAIMRB = 0x0000;                  /* enable desired EVA group B interrupts */
    /* 0 0 0 0 0 0 0 0
       | | | | | | | T2PINT EN
       | | | | | | T2CINT EN
       | | | | | T2UFINT EN
       | | | | T2OFINT EN
       | | | RESERVED
       | | RESERVED
       | RESERVED
       RESERVED
    */
    
    
*EVAIMRC = 0x0000;                  /* enable desired EVA group C interrupts */
    /* 0 0 0 0 0 0 0 0
       | | | | | | | CAP1INT  EN
       | | | | | | CAP2INT EN
       | | | | | CAP3INT EN
       | | | | RESERVED
       | | | RESERVED
       | | RESERVED
       | RESERVED
       RESERVED
    */

 /*** Setup ADC and  configuration ***/                                                
*GPTCONA = *GPTCONA|0x0080; 
	/*GPTCONA = *GPTCONA&0xFDEF;  */
	/**GPTCONA = 0x0000;  */
    /*  \ \ \ \,\ 0 0 0,1 0 \ \,0 0 0 0
      0 | | | | | | | | | | | | | | | T1PIN-|00 force low;   01 active low
      1 | | | | | | | | | | | | | | T1PIN---|10 active high; 11 force high
      2 | | | | | | | | | | | | | T2PIN-|00 force low;   01 active low
      3 | | | | | | | | | | | | T2PIN---|10 active high; 11 force high
      4 | | | | | | | | | | | RESERVED
      5 | | | | | | | | | | RESERVED 
      6 | | | | | | | | | TCOMPOE-enable compare output 
      7 | | | | | | | | T1TOADC-|00 no start;       01 uderflow int flag
      8 | | | | | | | T1TOADC---|10 period int flag 11 comp int flag 
      9 | | | | | | T2TOADC-| 00 no start;    01 uderflow int flag
      A | | | | | T2TOADC---|10 per int flag 11 comp int flag
      B | | | | RESERVED
      C | | | RESERVED
      D | | T1STAT-T1 status:0 dec;1 inc (Read only)
      E | T2STAT-T2 status:0 dec;1 inc   (Read only)
      F RESERVED
     */ 	

*ADCTRL1=0x4000;      /*reset ADC */
asm("NOP");

*ADCTRL1=0x0010;      
/*     
 bit 15        0:      Reserved;
 bit 14        0:      no action;
 bit 13-12     00:     Immediate stop on suspend; 
 bit 11-8      0000:   2 x Tclk
 bit 7         1:      Fclk = CLK/2,Tclk = 2 × (1/CLK)(example, for CLK = 30 MHz, Tclk = 66 ns)
 bit 6         0:      Start-stop mode..
 bit 5         0:      ADC interrupt request priority=high
 bit 4         0:      Dual-sequencer mode.
 bit 3         0:      Calibration mode disabled
 bit 2         0:      Full reference voltage is applied to the ADC input  
 bit 1         1:      VREFHI is used as precharge value at ADC input
 bit 0         0:      Self-test mode disabled   */  
 
 *ADCTRL2=0x8100;  
/*     
 bit 15        0:      No action
 bit 14        0:      0 No action
 bit 13        0:      Clears a pending SOC trigger.
 bit 12        0:      Sequencer is Idle (i.e., waiting for trigger)
 bit 11-10     01:     Interrupt requested immediately when INT FLAG SEQ1 flag is set
 bit 9         0:      This bit must be cleared by the user writing a 1 to it.
 bit 8         1:      Allows SEQ1/SEQ to be started by Event Manager A trigger.
 bit 7         0:      Disable External signal start-of-conversion bit for SEQ1
 bit 6         0:      No action  
 bit 5         0:      Clears a Pending SOC trigger.
 bit 4         0:      Sequencer is idle
 bit 3-2       01:     Interrupt requested immediate on INT FLAG SEQ2 flag set 
 bit 1         0:      No interrupt event.
 bit 0         0:      SEQ2 cannot be started by EVB trigger.  */    
 
 *MAX_CONV=0x000f;      /* Number of conversions=4*/  
 *CHSELSEQ1=0x3210; 
 *CHSELSEQ2=0x7654;
 *CHSELSEQ3=0xBA98;
 *CHSELSEQ4=0xFEDC; 
 
  
   
    
      *PFDATDIR = *PFDATDIR | 0x4000;      //IOPF6输出有效      
   *PADATDIR=*PADATDIR|0x8080;
 *PBDATDIR=*PBDATDIR|0x5A5A;
    *PBDATDIR=*PBDATDIR&0x5FFF;
   *PEDATDIR=*PEDATDIR|0xFEFE;
   *PFDATDIR=*PFDATDIR|0x1111;
    *PFDATDIR=*PFDATDIR&0xD1FF;
   *PADATDIR=*PADATDIR|0xFFFF;  //test
     *PADATDIR=*PADATDIR|0x2000;      //cap3
     asm(" setc INTM ");
  EnDrive();
  // DisDrive();
  GndCeptRes();
  //UpJzgEn();
  UpJzgEn();
 UpJcqEn();
   
 
 UpVtgRes();
 
 UpPrtRes();
  *IMR=*IMR|0x0001; 
  
  
 }