ac97.h

ICEExt for Driver Studio3.2的sourcecode

#define LVBCI                        BIT2     // Set whenever the codec has processed
                                              // the last buffer in the buffer list.
                                              // Will fire an interrupt if IOC bit is
                                              // set. Probably set after the last
                                              // sample in the last buffer is
                                              // processed.  W1TC

                                         
#define CELV                         BIT1     // Current buffer == last valid.
                                              // Bit is RO and remains set until LVI is
                                              // cleared.  Probably set up the start
                                              // of processing for the last buffer.


#define DCH                          BIT0     // DMA controller halted.
                                              // set whenever audio stream is stopped
                                              // or something else goes wrong.


#define PI_PICB_REG                  0x08     // PCM in position in current buffer(RO)
#define PO_PICB_REG                  0x18     // PCM out position in current buffer(RO)
#define MC_PICB_REG                  0x28     // MIC in position in current buffer (RO)

// 16bit read only
// position in current buffer regs show the number of dwords left to be
// processed in the current buffer.

#define PI_PIV_REG                   0x0a     // PCM in Prefected index value
#define PO_PIV_REG                   0x1a     // PCM out Prefected index value
#define MC_PIV_REG                   0x2a     // MIC in Prefected index value

// 8bit, read only
// Prefetched index value register.
// tells which buffer number (0-31) has be prefetched.  I'd imagine this
// value follows the current index value fairly closely. (CIV+1)

#define PI_CR_REG                    0x0b     // PCM in Control Register
#define PO_CR_REG                    0x1b     // PCM out Control Register
#define MC_CR_REG                    0x2b     // MIC in Control Register

// 8bit
// Control register *MUST* only be accessed as an 8bit value.
// Control register.  See bitfields below.

#define IOCE                         BIT4     // interrupt on complete enable.
                                              // set this bit if you want an interrupt
                                              // to fire whenever LVBCI is set.

#define FEIFE                        BIT3     // set if you want an interrupt to fire
                                              // whenever there is a FIFO (over or
                                              // under) error.

#define LVBIE                        BIT2     // last valid buffer interrupt enable.
                                              // set if you want an interrupt to fire
                                              // whenever the completion of the last
                                              // valid buffer.

#define RR                           BIT1     // reset registers.  Nukes all regs
                                              // except bits 4:2 of this register.
                                              // Only set this bit if BIT 0 is 0

#define RPBM                         BIT0     // Run/Pause
                                              // set this bit to start the codec!


#define GLOB_CNT_REG                 0x2c     // Global control register
#define SEC_RES_EN                   BIT5     // secondary codec resume event 
                                              // interrupt enable.  Not used here.
#define PRI_RES_EN                   BIT4     // ditto for primary. Not used here.
#define ACLINK_OFF                   BIT3     // Turn off the AC97 link
#define ACWARM_RESET                 BIT2     // Awaken the AC97 link from sleep.
                                              // registers preserved, bit self clears
#define ACCOLD_RESET                 BIT1     // Reset everything in the AC97 and
                                              // reset all registers.  Not self clearing

#define GPIIE                        BIT0     // GPI Interrupt enable.
                                              // set if you want an interrupt to
                                              // fire upon ANY of the bits in the
                                              // GPI (general pursose inputs?) not used.

#define GLOB_STS_REG                 0x30     // Global Status register (RO)

#define MD3                          BIT17   // modem powerdown status (yawn)
#define AD3                          BIT16   // Audio powerdown status (yawn)
#define RD_COMPLETE_STS              BIT15   // Codec read timed out. 0=normal
#define BIT3SLOT12                   BIT14   // shadowed status of bit 3 in slot 12
#define BIT2SLOT12                   BIT13   // shadowed status of bit 2 in slot 12
#define BIT1SLOT12                   BIT12   // shadowed status of bit 1 in slot 12
#define SEC_RESUME_STS               BIT11   // secondary codec has resumed (and irqed)
#define PRI_RESUME_STS               BIT10   // primary codec has resumed (and irqed)
#define SEC_CODEC_RDY                BIT9    // secondary codec is ready for action
#define PRI_CODEC_RDY                BIT8    // Primary codec is ready for action
                                             // software must check these bits before
                                             // starting the codec!
#define MIC_IN_IRQ                   BIT7    // MIC in caused an interrupt
#define PCM_OUT_IRQ                  BIT6    // One of the PCM out channels IRQed
#define PCM_IN_IRQ                   BIT5    // One of the PCM in channels IRQed
#define MODEM_OUT_IRQ                BIT2    // modem out channel IRQed
#define MODEM_IN_IRQ                 BIT1    // modem in channel IRQed
#define GPI_STS_CHANGE               BIT0    // set whenever GPI's have changed.
                                             // BIT0 of slot 12 also reflects this.

#define ACC_SEMA_REG                 0x34    // Codec write semiphore register
#define CODEC_BUSY                   BIT0    // codec register I/O is happening
                                             // self clearing

//
// Buffer Descriptors List
// As stated earlier, each buffer descriptor list is a set of (up to) 32 
// descriptors, each 8 bytes in length.  Bytes 0-3 of a descriptor entry point
// to a chunk of memory to either play from or record to.  Bytes 4-7 of an
// entry describe various control things detailed below.
// 
// Buffer pointers must always be aligned on a Dword boundry.
//

#define IOC                          BIT31    // Fire an interrupt whenever this
                                              // buffer is complete.

#define BUP                          BIT30    // Buffer Underrun Policy.
                                              // if this buffer is the last buffer
                                              // in a playback, fill the remaining
                                              // samples with 0 (silence) or not.
                                              // It's a good idea to set this to 1
                                              // for the last buffer in playback,
                                              // otherwise you're likely to get a lot
                                              // of noise at the end of the sound.

//
// Bits 15:0 contain the length of the buffer, in number of samples, which
// are 16 bits each, coupled in left and right pairs, or 32bits each.
// Luckily for us, that's the same format as .wav files.
//
// A value of FFFF is 65536 samples.  Running at 44.1Khz, that's just about
// 1.5 seconds of sample time.  FFFF * 32bits is 1FFFFh bytes or 128k of data.
//
// A value of 0 in these bits means play no samples.
//

#define WAV_BUFFER_SIZE    0xFFF0        
extern UCHAR  *WAV_BUFFER1;           // pointer to the first  wav buffer 
extern UCHAR  *WAV_BUFFER2;           // pointer to the second wav buffer
extern ULONG  AC97_PCI_ADDRESS;       // AC97 PCI address


BOOL ac97_Init( VOID );
VOID ac97_Done( VOID );
VOID ac97_PrepareToPlay( VOID );
VOID ac97_CreateBDL( VOID );
VOID ac97_SetBDLAddress( VOID );
VOID ac97_Play( VOID );
VOID ac97_Stop( VOID );
VOID ac97_Loop( VOID );

VOID ac97_SetPcmFrontDacRate   ( USHORT dwRate );
VOID ac97_SetPcmSurroundDacRate( USHORT dwRate );
VOID ac97_SetMasterVolume      ( USHORT dwVolume );
VOID ac97_SetPcmOutVolume      ( USHORT dwVolume );
VOID ac97_ResetDMA( VOID );
VOID ac97_SetLastValidIndex( UCHAR dwLastIndex );
VOID ac97_SetNewIndex( VOID );
VOID ac97_UpdateLVI( VOID );
ULONG ac97_GetCurrentIndex( VOID );


#endif  __AC97_H__