ac97.h

ICEExt for Driver Studio3.2的sourcecode

/*++
    Copyright  (c) 2004 Sten
    Contact information:
        mail: [e-mail]

    This program is free software; you can redistribute it and/or
    modify it under the terms of the GNU General Public License
    as published by the Free Software Foundation; either version 2
    of the License, or (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.

 
Module Name:
    ac97.h

Abstract: AC'97 code functions 

Revision History:

 Sten        01/01/2004
      Initial release. Started expiriments on using AC'97.. Wow!!

--*/

#ifndef __AC97_H__
#define __AC97_H__

#include "pci.h"

#define INTEL_VID       0x8086           // Intel's PCI vendor ID
#define ICH_DID         0x2415           // ICH device ID
#define ICH0_DID        0x2425           // ICH0
#define ICH2_DID        0x2445           // ICH2  
#define ICH3_DID        0x2485           // ICH3 ?
#define ICH4_DID        0x24C5           // ICH4
#define ICH5_DID        0x24D5           // ICH5 ?
                                         // they all should be compatible.

#define NAMBAR_REG      0x10             // native audio mixer BAR
#define NAM_SIZE        256              // 256 bytes required.

#define NABMBAR_REG     0x14             // native audio bus mastering BAR
#define NABM_SIZE       64               // 64 bytes

#define INTLINE_REG     0x3C             // interrupt line register


/*
Codec registers.

Not all codecs are created equal. Refer to the spec for your specific codec.

All registers are 16bits wide.  Access to codec registers over the AC97 link
is defined by the OEM.  

Secondary codec's are accessed by ORing in BIT7 of all register accesses.

*/

// each codec/mixer register is 16bits

#define CODEC_RESET_REG                      0x00     // reset codec
#define CODEC_MASTER_VOL_REG                 0x02     // master volume
#define CODEC_HP_VOL_REG                     0x04     // headphone volume
#define CODEC_MASTER_MONO_VOl_REG            0x06     // master mono volume
#define CODEC_MASTER_TONE_REG                0x08     // master tone (R+L)
#define CODEC_PCBEEP_VOL_REG                 0x0a     // PC beep volume
#define CODEC_PHONE_VOL_REG                  0x0b     // phone volume
#define CODEC_MIC_VOL_REG                    0x0e     // MIC volume
#define CODEC_LINE_IN_VOL_REG                0x10     // line input volume
#define CODEC_CD_VOL_REG                     0x12     // CD volume
#define CODEC_VID_VOL_REG                    0x14     // video volume
#define CODEC_AUX_VOL_REG                    0x16     // aux volume
#define CODEC_PCM_OUT_REG                    0x18     // PCM output volume
#define CODEC_RECORD_SELECT_REG              0x1a     // record select input
#define CODEC_RECORD_VOL_REG                 0x1c     // record volume
#define CODEC_RECORD_MIC_VOL_REG             0x1e     // record mic volume
#define CODEC_GP_REG                         0x20     // general purpose
#define CODEC_3D_CONTROL_REG                 0x22     // 3D control
// 24h is reserved
#define CODEC_POWER_CTRL_REG                 0x26     // powerdown control
#define CODEC_EXT_AUDIO_REG                  0x28     // extended audio
#define CODEC_EXT_AUDIO_CTRL_REG             0x2a     // extended audio control
#define CODEC_PCM_FRONT_DACRATE_REG          0x2c     // PCM out sample rate
#define CODEC_PCM_SURND_DACRATE_REG          0x2e     // surround sound sample rate
#define CODEC_PCM_LFE_DACRATE_REG            0x30     // LFE sample rate
#define CODEC_LR_ADCRATE_REG                 0x32     // PCM in sample rate
#define CODEC_MIC_ADCRATE_REG                0x34     // mic in sample rate

// registers 36-7a are reserved on the ICH

#define CODEC_VENDORID1_REG                  0x7c     // codec vendor ID 1
#define CODEC_VENDORID2_REG                  0x7e     // codec vendor ID 2

// Mixer registers 0 through 51h reside in the ICH and are not forwarded over
// the AC97 link to the codec, which I think is a little weird.  Looks like
// the ICH makes it so you don't need a fully functional codec to play audio?
//
// whenever 2 codecs are present in the system, use BIT7 to access the 2nd
// set of registers, ie 80h-feh

#define PRIMARY_CODEC                        0       // 0-7F for primary codec
#define SECONDARY_CODEC                      BIT7    // 80-8f registers for 2ndary
                                        
#define SAMPLE_RATE_441khz                  44100    // 44.1Khz  (cd quality) rate

// BUS master registers, accessed via NABMBAR+offset

// ICH supports 3 different types of register sets for three types of things
// it can do, thus:
//
// PCM in (for recording) aka PI
// PCM out (for playback) aka PO
// MIC in (for recording) aka MC

#define PI_BDBAR_REG                 0x00     // PCM in buffer descriptor BAR
#define PO_BDBAR_REG                 0x10     // PCM out buffer descriptor BAR
#define MC_BDBAR_REG                 0x20     // MIC in buffer descriptor BAR

// each buffer descriptor BAR holds a pointer which has entries to the buffer
// contents of the .WAV file we're going to play.  Each entry is 8 bytes long
// (more on that later) and can contain 32 entries total, so each BAR is
// 256 bytes in length, thus:

#define BDL_SIZE                     (32*8)   // Buffer Descriptor List size
#define INDEX_MASK                   31       // indexes must be 0-31

#define PI_CIV_REG                   0x04     // PCM in current Index value (RO)
#define PO_CIV_REG                   0x14     // PCM out current Index value (RO)
#define MC_CIV_REG                   0x24     // MIC in current Index value (RO)

// 8bit read only
// each current index value is simply a pointer showing us which buffer
// (0-31) the codec is currently processing.  Once this counter hits 31, it
// wraps back to 0.
// this can be handy to know, as once it hits 31, we're almost out of data to
// play back or room to record!

#define PI_LVI_REG                   0x05     // PCM in Last Valid Index
#define PO_LVI_REG                   0x15     // PCM out Last Valid Index
#define MC_LVI_REG                   0x25     // MIC in Last Valid Index

// 8bit read/write
// The Last Valid Index is a number (0-31) to let the codec know what buffer
// number to stop on after processing.  It could be very nasty to play audio
// from buffers that aren't filled with the audio we want to play.

#define PI_SR_REG                    0x06     // PCM in Status register
#define PO_SR_REG                    0x16     // PCM out Status register
#define MC_SR_REG                    0x26     // MIC in Status register

// 16bit read/write
// status registers.  Bitfields follow:

#define FIFO_ERR                     BIT4     // FIFO Over/Underrun W1TC.

#define BCIS                         BIT3     // buffer completion interrupt status.
                                              // Set whenever the last sample in ANY
                                              // buffer is finished.  Bit is only
                                              // set when the Interrupt on Complete
                                              // (BIT4 of control reg) is set.