csl_cachel1.c

Dm6455 driver,magbe useful to you!

 *
 *   <b> Post Condition </b>
 *   @n  Writeback L1D cache
 *
 *   @b Modifies
 *   @n L1DWWC and L1DWBAR registers
 *
 *   @b Example
 *   @verbatim
        ...
        CACHE_wbL1d((Uint32*)(0x1000), 200, CACHE_NOWAIT);
        ...
     @endverbatim
 *  ============================================================================
 */
#pragma CODE_SECTION (CACHE_wbL1d, ".text:csl_section:cache");
void CACHE_wbL1d (
    void            *blockPtr,
    Uint32          byteCnt,
    CACHE_Wait      wait
)
{
    CACHE_waitInternal();
    
    /* Critical section */
    asm(" dint");
    
    ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DWBAR = (Uint32)blockPtr;
    ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DWWC =((byteCnt+3)>>2);
    _CSL_cachebusyState = CACHE_WAIT_L1DWB;
    _CSL_cacheEmifState = (CACHE_emifState) \
                        (CSL_CACHE_EMIF_ISRANGE((Uint32)blockPtr) 
                             + CSL_CACHE_EMIF_ISEMIFBRANGE((Uint32)blockPtr));
    
    /* End critical section  */
    asm(" rint");
    
    if (wait)
        _CACHE_wait(wait);
}

/** ============================================================================
 *   @n@b CACHE_invL1d
 *
 *   @b Description
 *   @n Invalidates range specified in L1D.
 *   @n As per the specification,
 *   @n a. The start of the range that needs to be invalidated is written
 *         into L1DIBAR.
 *   @n b. The byte count is programmed in L1DIWC.
 *
 *   @b Arguments
 *   @verbatim
            blockPtr      Start address of range to be invalidated

            byteCnt       Number of bytes to be invalidated

            wait          Whether the call is blocking (and the extent of wait)
                          till the issued operation is completed.
                          Whether the function must exit on completion/or not.
     @endverbatim
 *
 *   <b> Return Value </b>
 *   @n  None
 *
 *   <b> Pre Condition </b>
 *   @n  The CACHE must be succesfully enabled via CACHE_enableCaching() before 
 *       calling this function.
 *
 *   <b> Post Condition </b>
 *   @n  Invalidate the L1D cache
 *
 *   @b Modifies
 *   @n L1DIWC and L1DIBAR registers
 *
 *   @b Example
 *   @verbatim
        ...
        CACHE_invL1d ((Uint32*)(0x1000), 200, CACHE_NOWAIT);
        ...
     @endverbatim
 *  ============================================================================
 */
#pragma CODE_SECTION (CACHE_invL1d, ".text:csl_section:cache");
void CACHE_invL1d (
    void         *blockPtr,
    Uint32       byteCnt,
    CACHE_Wait   wait
)
{
     
    CACHE_waitInternal();
    
    /* critical section */
    asm(" dint");
    
    ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DIBAR = (Uint32)blockPtr;
    ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DIWC = ((byteCnt+3)>>2);
    _CSL_cachebusyState = CACHE_WAIT_L1DINV;
    
    /* End critical section */
    asm(" rint");
    
    if (wait)
        _CACHE_wait(wait);
}

/** ============================================================================
 *   @n@b CACHE_wbInvL1d
 *
 *   @b Description
 *   @n Writeback invalidates range specified in L1D.
 *   @n As per the specification,
 *   @n a. The start of the range that needs to be writeback invalidated is
 *         programmed into L1DWIBAR.
 *   @n b. The byte count is programmed in L1DWIWC.
 *
 *   @b Arguments
 *   @verbatim
            blockPtr      Start address of range to be written back invalidated

            byteCnt       Number of bytes to be written back invalidated

            wait          Whether the call is blocking (and the extent of wait)
                          till the issued operation is completed.
                          Whether the function must exit on completion/or not.
     @endverbatim
 *
 *   <b> Return Value </b>
 *   @n  None
 *
 *   <b> Pre Condition </b>
 *   @n  The CACHE must be succesfully enabled via CACHE_enableCaching() before 
 *       calling this function.
 *
 *   <b> Post Condition </b>
 *   @n  Witebacvk and invalidate the L1D cache
 *
 *   @b Modifies
 *   @n L1DWIWC and L1DWIBAR registers
 *
 *   @b Example
 *   @verbatim
        ...
        CACHE_wbInvL1d ((Uint32*)(0x1000),200,CACHE_NOWAIT);
        ...
     @endverbatim
 *  ============================================================================
 */
#pragma CODE_SECTION (CACHE_wbInvL1d, ".text:csl_section:cache");
void CACHE_wbInvL1d (
    void         *blockPtr,
    Uint32       byteCnt,
    CACHE_Wait   wait
)
{
    CACHE_waitInternal();
    
    /* critical section */
    asm(" dint");
    
    ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DWIBAR = (Uint32)blockPtr;
    ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DWIWC = ((byteCnt+3)>>2);
    _CSL_cachebusyState = CACHE_WAIT_L1DWBINV;
    _CSL_cacheEmifState = (CACHE_emifState) \
                        (CSL_CACHE_EMIF_ISRANGE((Uint32)blockPtr) \
                            + CSL_CACHE_EMIF_ISEMIFBRANGE((Uint32)blockPtr));
                            
    /* End critical section */
    asm(" rint");
        
    if (wait)
        _CACHE_wait(wait);
}

/** ============================================================================
 *   @n@b CACHE_wbAllL1d
 *
 *   @b Description
 *   @n Writeback All of L1D.
 *   @n As per the specification,
 *   @n a. The L1DWB is programmed.
 *
 *   @b Arguments
 *   @verbatim
            wait          Whether the call is blocking (and the extent of wait)
                          till the issued operation is completed.
                          Whether the function must exit on completion/or not.
     @endverbatim
 *
 *   <b> Return Value </b>
 *   @n  None
 *
 *   <b> Pre Condition </b>
 *   @n  The CACHE must be succesfully enabled via CACHE_enableCaching() before 
 *       calling this function.
 *
 *   <b> Post Condition </b>
 *   @n  Writeback all the L1D cache
 *
 *   @b Modifies
 *   @n L1DWB register
 *
 *   @b Example
 *   @verbatim
        ...
        CACHE_wbAllL1d (CACHE_NOWAIT);
        ...
     @endverbatim
 *  ============================================================================
 */
#pragma CODE_SECTION (CACHE_wbAllL1d, ".text:csl_section:cache");
void CACHE_wbAllL1d (
    CACHE_Wait     wait
)
{
    CACHE_waitInternal();
    
    /* critical section */
    asm(" dint");
    
    ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DWB = 1;
    _CSL_cachebusyState = CACHE_WAIT_L1DWBALL;  
    _CSL_cacheEmifState = CACHE_EMIF_AB;
    
    /*  End critical section */
    asm(" rint");
    
    if (wait)
        _CACHE_wait(wait);
}

/** ============================================================================
 *   @n@b CACHE_invAllL1d
 *
 *   @b Description
 *   @n Invalidates All of L1D.
 *   @n As per the specification,
 *   @n a. The L1DINV is programmed.
 *
 *   @b Arguments
 *   @verbatim
            wait          Whether the call is blocking (and the extent of wait)
                          till the issued operation is completed.
                          Whether the function must exit on completion/or not.
     @endverbatim
 *
 *   <b> Return Value </b>
 *   @n  None
 *
 *   <b> Pre Condition </b>
 *   @n  The CACHE must be succesfully enabled via CACHE_enableCaching() before 
 *       calling this function.
 *
 *   <b> Post Condition </b>
 *   @n  Invalidate the all L1D cache
 *
 *   @b Modifies
 *   @n L1DINV register
 *
 *   @b Example
 *   @verbatim
        ...
        CACHE_invAllL1d (CACHE_NOWAIT);
        ...
     @endverbatim
 *  ============================================================================
 */
#pragma CODE_SECTION (CACHE_invAllL1d, ".text:csl_section:cache");
void CACHE_invAllL1d (
    CACHE_Wait    wait
)
{
    CACHE_waitInternal();
    
    /* critical section */
    asm(" dint"); 
      
    ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DINV = 1;
    _CSL_cachebusyState = CACHE_WAIT_L1DINVALL;
    
    /* End critical section */
    asm(" rint");
    
    if (wait)
        _CACHE_wait(wait);
}

/** ============================================================================
 *   @n@b CACHE_wbInvAllL1d
 *
 *   @b Description
 *   @n Writeback invalidates All of L1D.
 *   @n As per the specification,
 *   @n a. The L1DWBINV is programmed.
 *
 *   @b Arguments
 *   @verbatim
            wait          Whether the call is blocking (and the extent of wait)
                          till the issued operation is completed.
                          Whether the function must exit on completion/or not.
     @endverbatim
 *
 *   <b> Return Value </b>
 *   @n  None
 *
 *   <b> Pre Condition </b>
 *   @n  The CACHE must be succesfully enabled via CACHE_enableCaching() before 
 *       calling this function.
 *
 *   <b> Post Condition </b>
 *   @n  Writeback and invalidate all L1D cache
 *
 *   @b Modifies
 *   @n L1DWBINV register
 *
 *   @b Example
 *   @verbatim
        ...
        CACHE_wbInvAllL1d (CACHE_NOWAIT);
        ...
     @endverbatim
 *  ============================================================================
 */
#pragma CODE_SECTION (CACHE_wbInvAllL1d, ".text:csl_section:cache");
void CACHE_wbInvAllL1d (
    CACHE_Wait      wait
)
{
     
    CACHE_waitInternal();
    
    /* critical section */
    asm(" dint");
    
    ((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DWBINV = 1;
    _CSL_cachebusyState = CACHE_WAIT_L1DWBINVALL;
    _CSL_cacheEmifState = CACHE_EMIF_AB;
    
    /* End of critical section */
    asm(" rint");
    
    if (wait)
        _CACHE_wait(wait);
}