csl_sriogethwsetup.c

Dm6455 driver,magbe useful to you!

                /* Get the polarity configuration */
                hwSetup->serDesRxChannelCfg [i].invertedPolarity = 
                    CSL_FEXT (hSrio->regs->SERDES_CFGRX_CNTL[i], 
                    SRIO_SERDES_CFGRX_CNTL_INVPAIR);

                /* Get the termination configuration */
                hwSetup->serDesRxChannelCfg [i].termination = 
                    (CSL_SrioSerDesTermination) CSL_FEXT (
                    hSrio->regs->SERDES_CFGRX_CNTL[i], 
                    SRIO_SERDES_CFGRX_CNTL_TERM);

                /* Get the symbol alignment configuration */
                hwSetup->serDesRxChannelCfg [i].symAlign = 
                    (CSL_SrioSerDesSymAlignment) CSL_FEXT (
                    hSrio->regs->SERDES_CFGRX_CNTL[i], 
                    SRIO_SERDES_CFGRX_CNTL_ALIGN);

                /* Get the loss of signal detection configuration */
                hwSetup->serDesRxChannelCfg [i].los = 
                    (CSL_SrioSerDesLos) CSL_FEXT (
                    hSrio->regs->SERDES_CFGRX_CNTL[i], 
                    SRIO_SERDES_CFGRX_CNTL_LOS);

                /* Get the clock and data recovery algorithm configuration */
                hwSetup->serDesRxChannelCfg [i].clockDataRecovery = 
                    CSL_FEXT (hSrio->regs->SERDES_CFGRX_CNTL[i], 
                    SRIO_SERDES_CFGRX_CNTL_CDR);

                /* Get the adaptive equalizer configuration */
                hwSetup->serDesRxChannelCfg [i].equalizer = 
                    CSL_FEXT (hSrio->regs->SERDES_CFGRX_CNTL[i], 
                    SRIO_SERDES_CFGRX_CNTL_EQ);
            }
        }

        /* SERDES TX channel enable setup */
        for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
            /* Get the transmitter enable configuration */
            hwSetup->serDesTxChannelCfg [i].enTx = 
                CSL_FEXT (hSrio->regs->SERDES_CFGTX_CNTL[i],
                SRIO_SERDES_CFGTX_CNTL_ENTX);

            if (hwSetup->serDesTxChannelCfg [i].enTx) {
                /* Get the bus width configuration */
                hwSetup->serDesTxChannelCfg [i].busWidth = 
                    (CSL_SrioSerDesBusWidth) CSL_FEXT (
                    hSrio->regs->SERDES_CFGTX_CNTL[i],
                    SRIO_SERDES_CFGTX_CNTL_BUSWIDTH);

                /* Get the operating rate configuration */
                hwSetup->serDesTxChannelCfg [i].rate = 
                    (CSL_SrioSerDesRate) CSL_FEXT (
                    hSrio->regs->SERDES_CFGTX_CNTL[i],
                    SRIO_SERDES_CFGTX_CNTL_RATE);

                /* Get the polarity configuration */
                hwSetup->serDesTxChannelCfg [i].invertedPolarity = 
                    CSL_FEXT (hSrio->regs->SERDES_CFGTX_CNTL[i],
                    SRIO_SERDES_CFGTX_CNTL_INVPAIR);

                /* Get the common mode configuration */
                hwSetup->serDesTxChannelCfg [i].commonMode = 
                    (CSL_SrioSerDesCommonMode) CSL_FEXT (
                    hSrio->regs->SERDES_CFGTX_CNTL[i],
                    SRIO_SERDES_CFGTX_CNTL_CM);

                /* Get the output swing configuration */
                hwSetup->serDesTxChannelCfg [i].outputSwing = 
                    (CSL_SrioSerDesSwingCfg) CSL_FEXT (
                    hSrio->regs->SERDES_CFGTX_CNTL[i],
                    SRIO_SERDES_CFGTX_CNTL_SWING);

                /* Get the output de-emphasis configuration */
                hwSetup->serDesTxChannelCfg [i].outputDeEmphasis = 
                    CSL_FEXT (hSrio->regs->SERDES_CFGTX_CNTL[i],
                    SRIO_SERDES_CFGTX_CNTL_DE);

                /* Get the fixed phase configuration */
                hwSetup->serDesTxChannelCfg [i].enableFixedPhase = 
                    CSL_FEXT (hSrio->regs->SERDES_CFGTX_CNTL[i],
                    SRIO_SERDES_CFGTX_CNTL_ENFTP);
            }
        }

        /* get flow control setup */
        for (i = 0; i < CSL_SRIO_FLOW_CONTROL_REG_MAX; i++) {
            hwSetup->flowCntlIdLen[i] = (Bool)CSL_FEXT(
                     hSrio->regs->FLOW_CNTL[i], SRIO_FLOW_CNTL_TT);

            hwSetup->flowCntlId[i] = CSL_FEXT(
                     hSrio->regs->FLOW_CNTL[i], SRIO_FLOW_CNTL_FLOW_CNTL_ID);
        }

        /* get the processing element address bits setup */
        hwSetup->peLlAddrCtrl = (CSL_SrioAddrSelect)hSrio->regs->PE_LL_CTL;

        /* get Base device configuration */
        hwSetup->devIdSetup.smallTrBaseDevId = CSL_FEXT(
                 hSrio->regs->BASE_ID, SRIO_BASE_ID_BASE_DEVICEID);

        hwSetup->devIdSetup.largeTrBaseDevId = CSL_FEXT(
                 hSrio->regs->BASE_ID, SRIO_BASE_ID_LARGE_BASE_DEVICEID);

        hwSetup->devIdSetup.hostBaseDevId = CSL_FEXT(
                            hSrio->regs->HOST_BASE_ID_LOCK, 
                            SRIO_HOST_BASE_ID_LOCK_HOST_BASE_DEVICEID);

        /* get Software defined component Tag for PE (processing element) */
        hwSetup->componentTag = hSrio->regs->COMP_TAG;

        /* Port General configuration */
        hwSetup->portGenSetup.portLinkTimeout = CSL_FEXT(
                 hSrio->regs->SP_LT_CTL, SRIO_SP_LT_CTL_TIMEOUT_VALUE);

        hwSetup->portGenSetup.portRespTimeout = CSL_FEXT(
                 hSrio->regs->SP_RT_CTL, SRIO_SP_RT_CTL_TIMEOUT_VALUE);

        hwSetup->portGenSetup.hostEn = (Bool)CSL_FEXT(
                            hSrio->regs->SP_GEN_CTL, SRIO_SP_GEN_CTL_HOST);

        hwSetup->portGenSetup.masterEn = (Bool)CSL_FEXT(
                    hSrio->regs->SP_GEN_CTL, SRIO_SP_GEN_CTL_MASTER_ENABLE);

        /* get port control configuration */
        for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
            hwSetup->portCntlSetup[i].portDis = (Bool)CSL_FEXT(
                        hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_PORT_DISABLE);

            hwSetup->portCntlSetup[i].outPortEn = (Bool)CSL_FEXT(
                hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_OUTPUT_PORT_ENABLE);

            hwSetup->portCntlSetup[i].inPortEn = (Bool)CSL_FEXT(
                hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_INPUT_PORT_ENABLE);

            hwSetup->portCntlSetup[i].portWidthOverride = 
                (CSL_SrioPortWidthOverride)CSL_FEXT(hSrio->regs->PORT[i].SP_CTL,
                                            SRIO_SP_CTL_PORT_WIDTH_OVERRIDE);

            hwSetup->portCntlSetup[i].errCheckDis = (Bool)CSL_FEXT(
                hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_ERROR_CHECK_DISABLE);

            hwSetup->portCntlSetup[i].multicastRcvEn = (Bool)CSL_FEXT(
                hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_MULTICAST_PARTICIPANT);

            hwSetup->portCntlSetup[i].stopOnPortFailEn = (Bool)CSL_FEXT(
                hSrio->regs->PORT[i].SP_CTL, 
                SRIO_SP_CTL_STOP_PORT_FLD_ENC_ENABLE);

            hwSetup->portCntlSetup[i].dropPktEn = (Bool)CSL_FEXT(
                hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_DROP_PACKET_ENABLE);

            hwSetup->portCntlSetup[i].portLockoutEn = (Bool)CSL_FEXT(
                hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_PORT_LOCKOUT);	
        }

        /* get logical/transport layer errors setup */
        hwSetup->lgclTransErrEn = hSrio->regs->ERR_EN;

        /* get port error configuration */
        for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
            hwSetup->portErrSetup[i].portErrRateEn = 
                            hSrio->regs->PORT_ERROR[i].SP_RATE_EN;

            hwSetup->portErrSetup[i].prtErrRtBias = 
             (CSL_SrioErrRtBias)CSL_FEXT(hSrio->regs->PORT_ERROR[i].SP_ERR_RATE, 
                    SRIO_SP_ERR_RATE_ERROR_RATE_BIAS);

            hwSetup->portErrSetup[i].portErrRtRec = (CSL_SrioErrRtNum)CSL_FEXT(
                    hSrio->regs->PORT_ERROR[i].SP_ERR_RATE, 
                    SRIO_SP_ERR_RATE_ERROR_RATE_RECOVERY);

            hwSetup->portErrSetup[i].portErrRtFldThresh = CSL_FEXT(
                    hSrio->regs->PORT_ERROR[i].SP_ERR_THRESH, 
                    SRIO_SP_ERR_THRESH_ERROR_RATE_FAILED_THRESHOLD);

            hwSetup->portErrSetup[i].portErrRtDegrdThresh = CSL_FEXT(
                    hSrio->regs->PORT_ERROR[i].SP_ERR_THRESH, 
                    SRIO_SP_ERR_THRESH_ERROR_RATE_DEGRADED_THRES);
        }

        /* get the discovery timer value */
        hwSetup->discoveryTimer = (CSL_SrioDiscoveryTimer)CSL_FEXT(
                        hSrio->regs->SP_IP_DISCOVERY_TIMER, 
                        SRIO_SP_IP_DISCOVERY_TIMER_DISCOVERY_TIMER);

        /* get the port write timer value */
        hwSetup->pwTimer = (CSL_SrioPwTimer)CSL_FEXT(
                        hSrio->regs->SP_IP_DISCOVERY_TIMER, 
                        SRIO_SP_IP_DISCOVERY_TIMER_PW_TIMER);

        /* get The configuration of SP_IP_MODE register */
        hwSetup->portIpModeSet = hSrio->regs->SP_IP_MODE;

        /* get The configuration of SP_IP_PRESCALE register */
        hwSetup->portIpPrescalar = CSL_FEXT(hSrio->regs->IP_PRESCAL, 
                                            SRIO_IP_PRESCAL_PRESCALE);

        /* ge the setups for silence timer and Port control independent error
         * register
         */
        for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
            hwSetup->silenceTimer[i] = (CSL_SrioSilenceTimer)CSL_FEXT(
                    hSrio->regs->PORT_OPTION[i].SP_SILENCE_TIMER, \
                                SRIO_SP_SILENCE_TIMER_SILENCE_TIMER);

            hwSetup->portCntlIndpEn[i] = 
                            hSrio->regs->PORT_OPTION[i].SP_CTL_INDEP;
        }
    }
    return (status);
}