csl_sriogethwsetup.c

Dm6455 driver,magbe useful to you!

/* ============================================================================
 * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
 *
 * Use of this software is controlled by the terms and conditions found in the
 * license agreement under which this software has been supplied.
 * =============================================================================
 */
/** ===========================================================================
 * @file csl_srioGetHwSetup.c
 *
 * @brief File for functional layer of CSL API CSL_srioGetHwSetup() 
 * 
 * @path $(CSLPATH)\srio\src
 *
 * @desc The CSL_srioGetHwSetup() function definition and it's associated 
 *       functions
 * ============================================================================
 */       
/* ============================================================================
 * Revision History
 * ===============
 * 25-Aug-2005 PSK File Created.
 * 15-Dec-2005 SD  Updated the SERDES configuration.  
 * ============================================================================
 */
#include <csl_srio.h>

/** ============================================================================
 *   @n@b CSL_srioGetHwSetup
 *
 *   @b Description
 *   @n It retrives the hardware setup parameters
 *
 *   @b Arguments
 *   @verbatim
            hSrio           Handle to the SRIO instance

            hwSetup         Pointer to hardware setup structure
     @endverbatim
 *
 *   <b> Return Value </b>  CSL_Status
 *   @li                    CSL_SOK             - Hardware setup retrived
 *   @li                    CSL_ESYS_BADHANDLE  - Invalid handle
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  The hardware set up structure will be populated with values from
 *       the registers
 *
 *   @b Modifies
 *   @n None
 *
 *   @b Example
 *   @verbatim
        CSL_status          status;
        CSL_SrioHwSetup     hwSetup;
        
        ...
        
        status = CSL_srioGetHwsetup(hSrio, &hwSetup);
        
        ...
     @endverbatim
 * ===========================================================================
 */
#pragma CODE_SECTION (CSL_srioGetHwSetup, ".text:csl_section:srio");
CSL_Status CSL_srioGetHwSetup (
    CSL_SrioHandle     hSrio,
    CSL_SrioHwSetup    *hwSetup
)
{
    int i;
    CSL_Status status = CSL_SOK;

    if (hSrio == NULL) {
        status = CSL_ESYS_BADHANDLE;
    }
    else if (hwSetup == NULL) {
        status = CSL_ESYS_INVPARAMS;
    }
    else {
        /* Get the peripheral enable/disable setup */
        hwSetup->perEn = (Bool)CSL_FEXT(hSrio->regs->PCR, SRIO_PCR_PEREN);

        /* Get the sleep/awake mode of memories while shut down */
        hwSetup->periCntlSetup.swMemSleepOverride = 
                    (Bool)CSL_FEXT(hSrio->regs->PER_SET_CNTL, 
                          SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE);

        /* Get the mode of operation, loopback/normal */
        hwSetup->periCntlSetup.loopback = 
            (Bool)CSL_FEXT(hSrio->regs->PER_SET_CNTL, 
            SRIO_PER_SET_CNTL_LOOPBACK);

        /* Get the setup of control ability to write any register during
         * initialization
         */
        hwSetup->periCntlSetup.bootComplete = 
         (Bool)CSL_FEXT(hSrio->regs->PER_SET_CNTL, 
                        SRIO_PER_SET_CNTL_BOOT_COMPLETE);

        /* get the setup of logical layer tx buffers needed to send the 
         * priority 2 packets
         */
        hwSetup->periCntlSetup.txPriority2Wm = (CSL_SrioTxPriorityWm)CSL_FEXT(
                 hSrio->regs->PER_SET_CNTL, SRIO_PER_SET_CNTL_TX_PRI2_WM);

        /* get the setup of logical layer tx buffers needed to send the 
         * priority 1 packets
         */
        hwSetup->periCntlSetup.txPriority1Wm = (CSL_SrioTxPriorityWm)CSL_FEXT(
                 hSrio->regs->PER_SET_CNTL, SRIO_PER_SET_CNTL_TX_PRI1_WM);

        /* get the setup of logical layer tx buffers needed to send the 
         * priority 0 packets
         */
        hwSetup->periCntlSetup.txPriority0Wm = (CSL_SrioTxPriorityWm)CSL_FEXT(
                 hSrio->regs->PER_SET_CNTL, SRIO_PER_SET_CNTL_TX_PRI0_WM);

        /* gwt Internal BUS transaction priority setup */
        hwSetup->periCntlSetup.busTransPriority = 
                 (CSL_SrioBusTransPriority)CSL_FEXT(hSrio->regs->PER_SET_CNTL, 
                  SRIO_PER_SET_CNTL_CBA_TRANS_PRI);

        /* get UDI buffering setup (priority versus port) setup */
        hwSetup->periCntlSetup.bufferMode = (CSL_SrioBufMode)CSL_FEXT(
                        hSrio->regs->PER_SET_CNTL, SRIO_PER_SET_CNTL_1X_MODE);

        /* get Internal clock frequency pre-scalar setup */
        hwSetup->periCntlSetup.prescalar = (CSL_SrioClkDiv)CSL_FEXT(
                hSrio->regs->PER_SET_CNTL, SRIO_PER_SET_CNTL_PRESCALER_SELECT);

        /* get pllc settings */
        hwSetup->periCntlSetup.pllEn = (Uint8)CSL_FEXTR(
                 hSrio->regs->PER_SET_CNTL, 3, 0);

        /* get global enable setup */
        hwSetup->gblEn = (Bool)CSL_FEXT(hSrio->regs->GBL_EN, SRIO_GBL_EN_EN);

        /* get block enable setup */
        for (i = 0; i < CSL_SRIO_BLOCKS_MAX; i++) {
            hwSetup->blkEn[i] = CSL_FEXT(hSrio->regs->BLK_ENABLE[i].BLK_EN, 
                                                            SRIO_BLK_EN_EN);
        }

        /* get the device ids setup */
        hwSetup->deviceId1 = hSrio->regs->DEVICEID_REG1;
        hwSetup->deviceId2 = hSrio->regs->DEVICEID_REG2;

        /* get the hardware packet forwading registers setup */
        for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
            hwSetup->pktFwdCntl[i].largeUpBoundDevId = CSL_FEXT(
                        hSrio->regs->HW_PKT_FWD[i].PF_16BIT_CNTL, 
                              SRIO_PF_16BIT_CNTL_16BIT_DEVID_UP_BOUND);

            hwSetup->pktFwdCntl[i].largeLowBoundDevId = CSL_FEXT(
                        hSrio->regs->HW_PKT_FWD[i].PF_16BIT_CNTL, 
                               SRIO_PF_16BIT_CNTL_16BIT_DEVID_LOW_BOUND);

            hwSetup->pktFwdCntl[i].outBoundPort = (CSL_SrioPortNum)CSL_FEXT(
                        hSrio->regs->HW_PKT_FWD[i].PF_8BIT_CNTL, 
                               SRIO_PF_8BIT_CNTL_OUT_BOUND_PORT);

            hwSetup->pktFwdCntl[i].smallUpBoundDevId = CSL_FEXT(
                        hSrio->regs->HW_PKT_FWD[i].PF_8BIT_CNTL, 
                                SRIO_PF_8BIT_CNTL_8BIT_DEVID_UP_BOUND);

            hwSetup->pktFwdCntl[i].smallLowBoundDevId = CSL_FEXT(
                                hSrio->regs->HW_PKT_FWD[i].PF_8BIT_CNTL, 
                                 SRIO_PF_8BIT_CNTL_8BIT_DEVID_LOW_BOUND);
        }

        /* SERDES PLL configuration setup */
        for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
            /* Get the enable pll configuration */
            hwSetup->serDesPllCfg[i].pllEnable = 
                CSL_FEXT (hSrio->regs->SERDES_CFG_CNTL[i], 
                    SRIO_SERDES_CFG_CNTL_ENPLL);

            if (hwSetup->serDesPllCfg[i].pllEnable) {
                /* Get the loop bandwidth configuration */
                hwSetup->serDesPllCfg[i].loopBandwidth = 
                    (CSL_SrioSerDesLoopBandwidth) CSL_FEXT (
                    hSrio->regs->SERDES_CFG_CNTL[i], 
                    SRIO_SERDES_CFG_CNTL_LB);

                /* Get the multiplication factor */
                hwSetup->serDesPllCfg[i].pllMplyFactor = 
                    (CSL_SrioSerDesPllMply) CSL_FEXT (
                    hSrio->regs->SERDES_CFG_CNTL[i], 
                    SRIO_SERDES_CFG_CNTL_MPY);
            }
        }

        /* SERDES RX channel enable setup */
        for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
            /* Get the receiver enabel configuration */
            hwSetup->serDesRxChannelCfg [i].enRx = 
                CSL_FEXT (hSrio->regs->SERDES_CFGRX_CNTL[i],
                SRIO_SERDES_CFGRX_CNTL_ENRX);

            if (hwSetup->serDesRxChannelCfg [i].enRx) {
                /* Get the bus width configuration */
                hwSetup->serDesRxChannelCfg [i].busWidth = 
                    (CSL_SrioSerDesBusWidth) CSL_FEXT (
                    hSrio->regs->SERDES_CFGRX_CNTL[i], 
                    SRIO_SERDES_CFGRX_CNTL_BUSWIDTH);

                /* Get the operating rate configuration */
                hwSetup->serDesRxChannelCfg [i].rate = 
                    (CSL_SrioSerDesRate) CSL_FEXT (
                    hSrio->regs->SERDES_CFGRX_CNTL[i], 
                    SRIO_SERDES_CFGRX_CNTL_RATE);