csl_sriohwsetup.c

Dm6455 driver,magbe useful to you!

                         SRIO_SERDES_CFGRX_CNTL_ALIGN, 
                         hwSetup->serDesRxChannelCfg [i].symAlign);

                /* Configure the loss of signal detection */
                CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], 
                         SRIO_SERDES_CFGRX_CNTL_LOS, 
                         hwSetup->serDesRxChannelCfg [i].los);

                /* Configure the clock and data recovery algorithm */
                CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], 
                         SRIO_SERDES_CFGRX_CNTL_CDR, 
                         hwSetup->serDesRxChannelCfg [i].clockDataRecovery);

                /* Configure the adaptive equalizer */
                CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], 
                         SRIO_SERDES_CFGRX_CNTL_EQ, 
                         hwSetup->serDesRxChannelCfg [i].equalizer);

                /* Enable the receiver */
                CSL_FINST(hSrio->regs->SERDES_CFGRX_CNTL[i],
                          SRIO_SERDES_CFGRX_CNTL_ENRX, ENABLE);
            }
        }

        /* SERDES TX channel enable setup */
        for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
            if (hwSetup->serDesTxChannelCfg [i].enTx) {
                /* Configure the bus width */
                CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i],
                    SRIO_SERDES_CFGTX_CNTL_BUSWIDTH,
                    hwSetup->serDesTxChannelCfg [i].busWidth);

                /* Configure the operating rate */
                CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i],
                    SRIO_SERDES_CFGTX_CNTL_RATE,
                    hwSetup->serDesTxChannelCfg [i].rate);

                /* Configure the polarity */
                CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i],
                    SRIO_SERDES_CFGTX_CNTL_INVPAIR,
                    hwSetup->serDesTxChannelCfg [i].invertedPolarity);

                /* Configure the common mode */
                CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i],
                    SRIO_SERDES_CFGTX_CNTL_CM,
                    hwSetup->serDesTxChannelCfg [i].commonMode);

                /* Configure the output swing */
                CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i],
                    SRIO_SERDES_CFGTX_CNTL_SWING,
                    hwSetup->serDesTxChannelCfg [i].outputSwing);

                /* Configure the output de-emphasis */
                CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i],
                    SRIO_SERDES_CFGTX_CNTL_DE,
                    hwSetup->serDesTxChannelCfg [i].outputDeEmphasis);

                /* Enable/disable the fixed phase */
                CSL_FINS (hSrio->regs->SERDES_CFGTX_CNTL[i],
                    SRIO_SERDES_CFGTX_CNTL_ENFTP,
                    hwSetup->serDesTxChannelCfg [i].enableFixedPhase);

                /* Enable the transmitter */
                CSL_FINST (hSrio->regs->SERDES_CFGTX_CNTL[i],
                    SRIO_SERDES_CFGTX_CNTL_ENTX, ENABLE);
            }
        }

        /* flow control setup */
        for (i = 0; i < CSL_SRIO_FLOW_CONTROL_REG_MAX; i++) {
            CSL_FINS(hSrio->regs->FLOW_CNTL[i], SRIO_FLOW_CNTL_TT, 
                                                hwSetup->flowCntlIdLen[i]);
            CSL_FINS(hSrio->regs->FLOW_CNTL[i], SRIO_FLOW_CNTL_FLOW_CNTL_ID, 
                                                hwSetup->flowCntlId[i]);
        }

        /* the processing element address bits setup */
        hSrio->regs->PE_LL_CTL = hwSetup->peLlAddrCtrl;

        /* Base device configuration */
        CSL_FINS(hSrio->regs->BASE_ID, SRIO_BASE_ID_BASE_DEVICEID, 
                                       hwSetup->devIdSetup.smallTrBaseDevId);

        CSL_FINS(hSrio->regs->BASE_ID, SRIO_BASE_ID_LARGE_BASE_DEVICEID, 
                                       hwSetup->devIdSetup.largeTrBaseDevId);

        CSL_FINS(hSrio->regs->HOST_BASE_ID_LOCK, 
                 SRIO_HOST_BASE_ID_LOCK_HOST_BASE_DEVICEID, 
                 hwSetup->devIdSetup.hostBaseDevId);

        /* Software defined component Tag for PE (processing element) setup */
        hSrio->regs->COMP_TAG = hwSetup->componentTag;


        /* Port General configuration */
        CSL_FINS(hSrio->regs->SP_LT_CTL, SRIO_SP_LT_CTL_TIMEOUT_VALUE, 
                 hwSetup->portGenSetup.portLinkTimeout);

        CSL_FINS(hSrio->regs->SP_RT_CTL, SRIO_SP_RT_CTL_TIMEOUT_VALUE, 
                 hwSetup->portGenSetup.portRespTimeout);

        CSL_FINS(hSrio->regs->SP_GEN_CTL, SRIO_SP_GEN_CTL_HOST, 
                 hwSetup->portGenSetup.hostEn);

        CSL_FINS(hSrio->regs->SP_GEN_CTL, SRIO_SP_GEN_CTL_MASTER_ENABLE, 
                 hwSetup->portGenSetup.masterEn);

        /* port control configuration */
        for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
            CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_PORT_DISABLE, 
                     hwSetup->portCntlSetup[i].portDis);

            CSL_FINS(hSrio->regs->PORT[i].SP_CTL, 
                     SRIO_SP_CTL_OUTPUT_PORT_ENABLE, 
                     hwSetup->portCntlSetup[i].outPortEn);

            CSL_FINS(hSrio->regs->PORT[i].SP_CTL, 
                     SRIO_SP_CTL_INPUT_PORT_ENABLE, 
                     hwSetup->portCntlSetup[i].inPortEn);

            CSL_FINS(hSrio->regs->PORT[i].SP_CTL, 
                     SRIO_SP_CTL_PORT_WIDTH_OVERRIDE, 
                     hwSetup->portCntlSetup[i].portWidthOverride);

            CSL_FINS(hSrio->regs->PORT[i].SP_CTL, 
                     SRIO_SP_CTL_ERROR_CHECK_DISABLE,
                     hwSetup->portCntlSetup[i].errCheckDis);

            CSL_FINS(hSrio->regs->PORT[i].SP_CTL, 
                     SRIO_SP_CTL_MULTICAST_PARTICIPANT, 
                     hwSetup->portCntlSetup[i].multicastRcvEn);

            CSL_FINS(hSrio->regs->PORT[i].SP_CTL, 
                     SRIO_SP_CTL_STOP_PORT_FLD_ENC_ENABLE,
                     hwSetup->portCntlSetup[i].stopOnPortFailEn);

            CSL_FINS(hSrio->regs->PORT[i].SP_CTL, 
                     SRIO_SP_CTL_DROP_PACKET_ENABLE,
                     hwSetup->portCntlSetup[i].dropPktEn);

            CSL_FINS(hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_PORT_LOCKOUT, 
                     hwSetup->portCntlSetup[i].portLockoutEn); 
        }

        /* logical/transport layer errors setup */
        hSrio->regs->ERR_EN = hwSetup->lgclTransErrEn;

        /* port error configuration */
        for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
            hSrio->regs->PORT_ERROR[i].SP_RATE_EN = 
                                       hwSetup->portErrSetup[i].portErrRateEn;

            CSL_FINS(hSrio->regs->PORT_ERROR[i].SP_ERR_RATE, 
                     SRIO_SP_ERR_RATE_ERROR_RATE_BIAS,
                     hwSetup->portErrSetup[i].prtErrRtBias);

            CSL_FINS(hSrio->regs->PORT_ERROR[i].SP_ERR_RATE, 
                     SRIO_SP_ERR_RATE_ERROR_RATE_RECOVERY, 
                     hwSetup->portErrSetup[i].portErrRtRec);

            CSL_FINS(hSrio->regs->PORT_ERROR[i].SP_ERR_THRESH, 
                     SRIO_SP_ERR_THRESH_ERROR_RATE_FAILED_THRESHOLD,
                     hwSetup->portErrSetup[i].portErrRtFldThresh);

            CSL_FINS(hSrio->regs->PORT_ERROR[i].SP_ERR_THRESH, 
                     SRIO_SP_ERR_THRESH_ERROR_RATE_DEGRADED_THRES, 
                     hwSetup->portErrSetup[i].portErrRtDegrdThresh);
        }

        /* the discovery timer value setup */
        CSL_FINS(hSrio->regs->SP_IP_DISCOVERY_TIMER, 
                 SRIO_SP_IP_DISCOVERY_TIMER_DISCOVERY_TIMER, 
                 hwSetup->discoveryTimer);

        /* port write timer value setup */
        CSL_FINS(hSrio->regs->SP_IP_DISCOVERY_TIMER, 
                 SRIO_SP_IP_DISCOVERY_TIMER_PW_TIMER, 
                 hwSetup->pwTimer);

        /* configuration of SP_IP_MODE register */
        hSrio->regs->SP_IP_MODE = hwSetup->portIpModeSet;

        /* configuration of SP_IP_PRESCALE register */
        CSL_FINS(hSrio->regs->IP_PRESCAL, SRIO_IP_PRESCAL_PRESCALE, 
                 hwSetup->portIpPrescalar);

        /* setups for silence timer and Port control independent error
         * register
         */
        for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
            CSL_FINS(hSrio->regs->PORT_OPTION[i].SP_SILENCE_TIMER, 
                     SRIO_SP_SILENCE_TIMER_SILENCE_TIMER, 
                     hwSetup->silenceTimer[i]);

            hSrio->regs->PORT_OPTION[i].SP_CTL_INDEP = 
                                        hwSetup->portCntlIndpEn[i];
        }

        /* Enable the peripheral */
        CSL_FINS(hSrio->regs->PCR, SRIO_PCR_PEREN, hwSetup->perEn);
    }
    return (status);
}