csl_sriohwsetup.c

Dm6455 driver,magbe useful to you!

/* ============================================================================
 * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
 *
 * Use of this software is controlled by the terms and conditions found in the
 * license agreement under which this software has been supplied.
 * ============================================================================
 */
/** ===========================================================================
 * @file csl_srioHwSetup.c
 *
 * @brief File for functional layer of CSL API CSL_srioHwSetup()
 * 
 * @path $(CSLPATH)\src\srio
 *
 * @desc The CSL_srioHwSetup() function definition and it's associated
 *       functions 
 * ============================================================================
 */
/* ============================================================================
 * Revision History
 * ===============
 * 25-Aug-2005 PSK File Created.
 * 15-Dec-2005 SD  Updated the SERDES configuration.  
 * 09-Aug-2006 NG  Moved the GBL_EN & BLK_ENABLE before setting PER_SET_CNTL.
 * ============================================================================
 */
#include <csl_srio.h>
#include <csl_srioAux.h>

/** ============================================================================
 *   @n@b CSL_srioHwSetup
 *
 *   @b Description
 *   @n It configures the  SRIO instance registers as per the values passed
 *      in the hardware setup structure.
 *
 *   @b Arguments
 *   @verbatim
            hSrio            Handle to the SRIO instance

            setup            Pointer to hardware setup structure
     @endverbatim
 *
 *   <b> Return Value </b>  CSL_Status
 *   @li                    CSL_SOK             - Hardware setup successful
 *   @li                    CSL_ESYS_BADHANDLE  - Invalid handle
 *   @li                    CSL_ESYS_INVPARAMS  - Hardware structure is not
 *                                                properly initialized
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  The specified instance will be setup according to value passed
 *
 *   @b Modifies
 *   @n Hardware registers for the specified instance
 *
 *   @b Example
 *   @verbatim
         CSL_SrioHandle         hSrio;
         CSL_SrioObj            srioObj;
         CSL_SrioHwSetup        hwSetup;
         CSL_Status             status;
         CSL_SrioControlSetup periSetup;     
         CSL_SrioBlkEn          blockSetup;
         CSL_SrioPktFwdCntl     pktFwdSetup;

         hwSetup.perEn = TRUE;
         periSetup.swMemSleepOverride = FALSE;
         periSetup.loopback = FALSE;
         . . .
         periSetup.prescalar = CSL_SRIO_CLK_PRESCALE_0;
         hwSetup.periCntlSetup = &periSetup;
         hwSetup.blkEn = &blockSetup;
         hwSetup.pktFwdCntl = &pktfwdSetup;
         ...
         
         hSrio = CSL_srioOpen (&srioObj, CSL_SRIO, NULL, &status);
         
         ...
         
         status = CSL_srioHwSetup(hSrio, &hwSetup);     

         ...
     @endverbatim
 * ===========================================================================
 */
#pragma CODE_SECTION(CSL_srioHwSetup, ".text:csl_section:srio");
CSL_Status  CSL_srioHwSetup (
    CSL_SrioHandle  hSrio,
    CSL_SrioHwSetup *hwSetup
)
{
    Uint32 i;
    CSL_Status status = CSL_SOK;

    if (hSrio == NULL) {
        status = CSL_ESYS_BADHANDLE;
    }
    else if (hwSetup == NULL) {
        status = CSL_ESYS_INVPARAMS;
    }
    else {
        /* global enable setup */
        CSL_FINS(hSrio->regs->GBL_EN, SRIO_GBL_EN_EN, hwSetup->gblEn);

        /* block enable setup */
        for (i = 0; i < CSL_SRIO_BLOCKS_MAX; i++) {
            CSL_FINS(hSrio->regs->BLK_ENABLE[i].BLK_EN, SRIO_BLK_EN_EN, 
                     hwSetup->blkEn[i]);
        }

        /* sets up the PER_SET_CNTL register */
        hSrio->regs->PER_SET_CNTL = 
                        CSL_FMK(SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE, \
                                hwSetup->periCntlSetup.swMemSleepOverride) |
                        CSL_FMK( SRIO_PER_SET_CNTL_LOOPBACK, \
                                 hwSetup->periCntlSetup.loopback) |
                        CSL_FMK(SRIO_PER_SET_CNTL_BOOT_COMPLETE, \
                                hwSetup->periCntlSetup.bootComplete) |
                        CSL_FMK(SRIO_PER_SET_CNTL_TX_PRI2_WM, \
                                hwSetup->periCntlSetup.txPriority2Wm) |
                        CSL_FMK(SRIO_PER_SET_CNTL_TX_PRI1_WM, \
                                hwSetup->periCntlSetup.txPriority1Wm) |
                        CSL_FMK(SRIO_PER_SET_CNTL_TX_PRI0_WM, \
                                hwSetup->periCntlSetup.txPriority0Wm) |
                        CSL_FMK(SRIO_PER_SET_CNTL_CBA_TRANS_PRI, \
                                hwSetup->periCntlSetup.busTransPriority) |
                        CSL_FMK(SRIO_PER_SET_CNTL_1X_MODE, \
                                hwSetup->periCntlSetup.bufferMode) |
                        CSL_FMK(SRIO_PER_SET_CNTL_PRESCALER_SELECT, \
                                hwSetup->periCntlSetup.prescalar) |
                        CSL_FMKR(3, 0, hwSetup->periCntlSetup.pllEn);

        /* the device ids setup */
        hSrio->regs->DEVICEID_REG1 = hwSetup->deviceId1;
        hSrio->regs->DEVICEID_REG2 = hwSetup->deviceId2;

        /* hardware packet forwading registers setup */
        for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
            CSL_FINS(hSrio->regs->HW_PKT_FWD[i].PF_16BIT_CNTL, 
                     SRIO_PF_16BIT_CNTL_16BIT_DEVID_UP_BOUND, 
                     hwSetup->pktFwdCntl[i].largeUpBoundDevId);

            CSL_FINS(hSrio->regs->HW_PKT_FWD[i].PF_16BIT_CNTL, 
                     SRIO_PF_16BIT_CNTL_16BIT_DEVID_LOW_BOUND,
                     hwSetup->pktFwdCntl[i].largeLowBoundDevId);

            CSL_FINS(hSrio->regs->HW_PKT_FWD[i].PF_8BIT_CNTL, 
                     SRIO_PF_8BIT_CNTL_OUT_BOUND_PORT, 
                     hwSetup->pktFwdCntl[i].outBoundPort);

            CSL_FINS(hSrio->regs->HW_PKT_FWD[i].PF_8BIT_CNTL, 
                     SRIO_PF_8BIT_CNTL_8BIT_DEVID_UP_BOUND,
                     hwSetup->pktFwdCntl[i].smallUpBoundDevId);

            CSL_FINS(hSrio->regs->HW_PKT_FWD[i].PF_8BIT_CNTL, 
                     SRIO_PF_8BIT_CNTL_8BIT_DEVID_LOW_BOUND, 
                     hwSetup->pktFwdCntl[i].smallLowBoundDevId);
        }

        /* SERDES PLL configuration setup */
        for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
            if (hwSetup->serDesPllCfg[i].pllEnable) {
                /* Configure the loop bandwidth */
                CSL_FINS (hSrio->regs->SERDES_CFG_CNTL[i], 
                    SRIO_SERDES_CFG_CNTL_LB, 
                    hwSetup->serDesPllCfg[i].loopBandwidth);

                /* Configure the multiplication factor */
                CSL_FINS (hSrio->regs->SERDES_CFG_CNTL[i], 
                    SRIO_SERDES_CFG_CNTL_MPY, 
                    hwSetup->serDesPllCfg[i].pllMplyFactor);

                /* Enable the internal PLL*/
                CSL_FINST (hSrio->regs->SERDES_CFG_CNTL[i], 
                    SRIO_SERDES_CFG_CNTL_ENPLL, ENABLE);
            }
        }

        /* SERDES RX channel enable setup */
        for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
            if (hwSetup->serDesRxChannelCfg [i].enRx) {
                /* Configure the bus width */
                CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], 
                         SRIO_SERDES_CFGRX_CNTL_BUSWIDTH, 
                         hwSetup->serDesRxChannelCfg [i].busWidth);

                /* Configure the operating rate */
                CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], 
                         SRIO_SERDES_CFGRX_CNTL_RATE, 
                         hwSetup->serDesRxChannelCfg [i].rate);

                /* Configure the polarity */
                CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], 
                         SRIO_SERDES_CFGRX_CNTL_INVPAIR, 
                         hwSetup->serDesRxChannelCfg [i].invertedPolarity);

                /* Configure the termination */
                CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i], 
                         SRIO_SERDES_CFGRX_CNTL_TERM, 
                         hwSetup->serDesRxChannelCfg [i].termination);

                /* Configure the symbol alignment */
                CSL_FINS(hSrio->regs->SERDES_CFGRX_CNTL[i],