📄 cslr_edma3cc.h
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/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_edma3cc.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for EDMA3CC
*/
#ifndef _CSLR_EDMA3CC_H_
#define _CSLR_EDMA3CC_H_
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Register Overlay Structure for DRA
\**************************************************************************/
typedef struct {
volatile Uint32 DRAE;
volatile Uint32 DRAEH;
} CSL_Edma3ccDraRegs;
/**************************************************************************\
* Register Overlay Structure for SHADOW
\**************************************************************************/
typedef struct {
volatile Uint32 ER;
volatile Uint32 ERH;
volatile Uint32 ECR;
volatile Uint32 ECRH;
volatile Uint32 ESR;
volatile Uint32 ESRH;
volatile Uint32 CER;
volatile Uint32 CERH;
volatile Uint32 EER;
volatile Uint32 EERH;
volatile Uint32 EECR;
volatile Uint32 EECRH;
volatile Uint32 EESR;
volatile Uint32 EESRH;
volatile Uint32 SER;
volatile Uint32 SERH;
volatile Uint32 SECR;
volatile Uint32 SECRH;
volatile Uint8 RSVD0[8];
volatile Uint32 IER;
volatile Uint32 IERH;
volatile Uint32 IECR;
volatile Uint32 IECRH;
volatile Uint32 IESR;
volatile Uint32 IESRH;
volatile Uint32 IPR;
volatile Uint32 IPRH;
volatile Uint32 ICR;
volatile Uint32 ICRH;
volatile Uint32 IEVAL;
volatile Uint8 RSVD1[4];
volatile Uint32 QER;
volatile Uint32 QEER;
volatile Uint32 QEECR;
volatile Uint32 QEESR;
volatile Uint32 QSER;
volatile Uint32 QSECR;
volatile Uint8 RSVD2[360];
} CSL_Edma3ccShadowRegs;
/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_Edma3ccShadowRegs *CSL_EdmaccShadowRegsOvly;
/**************************************************************************\
* Register Overlay Structure for PARAMSET
\**************************************************************************/
typedef struct {
volatile Uint32 OPT;
volatile Uint32 SRC;
volatile Uint32 A_B_CNT;
volatile Uint32 DST;
volatile Uint32 SRC_DST_BIDX;
volatile Uint32 LINK_BCNTRLD;
volatile Uint32 SRC_DST_CIDX;
volatile Uint32 CCNT;
} CSL_Edma3ccParamsetRegs;
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 PID;
volatile Uint32 CCCFG;
volatile Uint8 RSVD0[248];
volatile Uint32 DCHMAP[64];
volatile Uint32 QCHMAP[4];
volatile Uint8 RSVD1[48];
volatile Uint32 DMAQNUM[8];
volatile Uint32 QDMAQNUM;
volatile Uint8 RSVD2[32];
volatile Uint32 QUEPRI;
volatile Uint8 RSVD3[120];
volatile Uint32 EMR;
volatile Uint32 EMRH;
volatile Uint32 EMCR;
volatile Uint32 EMCRH;
volatile Uint32 QEMR;
volatile Uint32 QEMCR;
volatile Uint32 CCERR;
volatile Uint32 CCERRCLR;
volatile Uint32 EEVAL;
volatile Uint8 RSVD4[28];
CSL_Edma3ccDraRegs DRA[8];
volatile Uint32 QRAE[8];
volatile Uint8 RSVD5[96];
volatile Uint32 QUEEVTENTRY[4][16];
volatile Uint8 RSVD6[256];
volatile Uint32 QSTAT[4];
volatile Uint8 RSVD7[16];
volatile Uint32 QWMTHRA;
volatile Uint8 RSVD8[28];
volatile Uint32 CCSTAT;
volatile Uint8 RSVD9[444];
volatile Uint32 MPFAR;
volatile Uint32 MPFSR;
volatile Uint32 MPFCR;
volatile Uint32 MPPAG;
volatile Uint32 MPPA[8];
volatile Uint8 RSVD10[2000];
volatile Uint32 ER;
volatile Uint32 ERH;
volatile Uint32 ECR;
volatile Uint32 ECRH;
volatile Uint32 ESR;
volatile Uint32 ESRH;
volatile Uint32 CER;
volatile Uint32 CERH;
volatile Uint32 EER;
volatile Uint32 EERH;
volatile Uint32 EECR;
volatile Uint32 EECRH;
volatile Uint32 EESR;
volatile Uint32 EESRH;
volatile Uint32 SER;
volatile Uint32 SERH;
volatile Uint32 SECR;
volatile Uint32 SECRH;
volatile Uint8 RSVD11[8];
volatile Uint32 IER;
volatile Uint32 IERH;
volatile Uint32 IECR;
volatile Uint32 IECRH;
volatile Uint32 IESR;
volatile Uint32 IESRH;
volatile Uint32 IPR;
volatile Uint32 IPRH;
volatile Uint32 ICR;
volatile Uint32 ICRH;
volatile Uint32 IEVAL;
volatile Uint8 RSVD12[4];
volatile Uint32 QER;
volatile Uint32 QEER;
volatile Uint32 QEECR;
volatile Uint32 QEESR;
volatile Uint32 QSER;
volatile Uint32 QSECR;
volatile Uint8 RSVD13[3944];
CSL_Edma3ccShadowRegs SHADOW[8];
volatile Uint8 RSVD14[4096];
CSL_Edma3ccParamsetRegs PARAMSET[256];
} CSL_Edma3ccRegs;
/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_Edma3ccRegs *CSL_Edma3ccRegsOvly;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* PID */
#define CSL_EDMA3CC_PID_PID_MASK (0xFFFFFFFFu)
#define CSL_EDMA3CC_PID_PID_SHIFT (0x00000000u)
#define CSL_EDMA3CC_PID_PID_RESETVAL (0x40011B00u)
#define CSL_EDMA3CC_PID_RESETVAL (0x40011B00u)
/* CCCFG */
#define CSL_EDMA3CC_CCCFG_MP_EXIST_MASK (0x02000000u)
#define CSL_EDMA3CC_CCCFG_MP_EXIST_SHIFT (0x00000019u)
#define CSL_EDMA3CC_CCCFG_MP_EXIST_RESETVAL (0x00000001u)
/*----MP_EXIST Tokens----*/
#define CSL_EDMA3CC_CCCFG_MP_EXIST_INCLUDED (0x00000001u)
#define CSL_EDMA3CC_CCCFG_CHMAP_EXIST_MASK (0x01000000u)
#define CSL_EDMA3CC_CCCFG_CHMAP_EXIST_SHIFT (0x00000018u)
#define CSL_EDMA3CC_CCCFG_CHMAP_EXIST_RESETVAL (0x00000001u)
/*----CHMAP_EXIST Tokens----*/
#define CSL_EDMA3CC_CCCFG_CHMAP_EXIST_INCLUDED (0x00000001u)
#define CSL_EDMA3CC_CCCFG_NUM_REGN_MASK (0x00300000u)
#define CSL_EDMA3CC_CCCFG_NUM_REGN_SHIFT (0x00000014u)
#define CSL_EDMA3CC_CCCFG_NUM_REGN_RESETVAL (0x00000003u)
/*----NUM_REGN Tokens----*/
#define CSL_EDMA3CC_CCCFG_NUM_REGN_8 (0x00000003u)
#define CSL_EDMA3CC_CCCFG_NUM_EVQUE_MASK (0x00070000u)
#define CSL_EDMA3CC_CCCFG_NUM_EVQUE_SHIFT (0x00000010u)
#define CSL_EDMA3CC_CCCFG_NUM_EVQUE_RESETVAL (0x00000003u)
/*----NUM_EVQUE Tokens----*/
#define CSL_EDMA3CC_CCCFG_NUM_EVQUE_4 (0x00000003u)
#define CSL_EDMA3CC_CCCFG_NUM_PAENTRY_MASK (0x00007000u)
#define CSL_EDMA3CC_CCCFG_NUM_PAENTRY_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_CCCFG_NUM_PAENTRY_RESETVAL (0x00000004u)
/*----NUM_PAENTRY Tokens----*/
#define CSL_EDMA3CC_CCCFG_NUM_PAENTRY_256 (0x00000004u)
#define CSL_EDMA3CC_CCCFG_NUM_INTCH_MASK (0x00000700u)
#define CSL_EDMA3CC_CCCFG_NUM_INTCH_SHIFT (0x00000008u)
#define CSL_EDMA3CC_CCCFG_NUM_INTCH_RESETVAL (0x00000004u)
/*----NUM_INTCH Tokens----*/
#define CSL_EDMA3CC_CCCFG_NUM_INTCH_64 (0x00000004u)
#define CSL_EDMA3CC_CCCFG_NUM_QDMACH_MASK (0x00000070u)
#define CSL_EDMA3CC_CCCFG_NUM_QDMACH_SHIFT (0x00000004u)
#define CSL_EDMA3CC_CCCFG_NUM_QDMACH_RESETVAL (0x00000002u)
/*----NUM_QDMACH Tokens----*/
#define CSL_EDMA3CC_CCCFG_NUM_QDMACH_4 (0x00000002u)
#define CSL_EDMA3CC_CCCFG_NUM_DMACH_MASK (0x00000007u)
#define CSL_EDMA3CC_CCCFG_NUM_DMACH_SHIFT (0x00000000u)
#define CSL_EDMA3CC_CCCFG_NUM_DMACH_RESETVAL (0x00000005u)
/*----NUM_DMACH Tokens----*/
#define CSL_EDMA3CC_CCCFG_NUM_DMACH_64 (0x00000005u)
#define CSL_EDMA3CC_CCCFG_RESETVAL (0x03334425u)
/* DCHMAP */
#define CSL_EDMA3CC_DCHMAP_PAENTRY_MASK (0x00003FE0u)
#define CSL_EDMA3CC_DCHMAP_PAENTRY_SHIFT (0x00000005u)
#define CSL_EDMA3CC_DCHMAP_PAENTRY_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DCHMAP_RESETVAL (0x00000000u)
/* QCHMAP */
#define CSL_EDMA3CC_QCHMAP_PAENTRY_MASK (0x00003FE0u)
#define CSL_EDMA3CC_QCHMAP_PAENTRY_SHIFT (0x00000005u)
#define CSL_EDMA3CC_QCHMAP_PAENTRY_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QCHMAP_TRWORD_MASK (0x0000001Cu)
#define CSL_EDMA3CC_QCHMAP_TRWORD_SHIFT (0x00000002u)
#define CSL_EDMA3CC_QCHMAP_TRWORD_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QCHMAP_RESETVAL (0x00000000u)
/* DMAQNUM */
#define CSL_EDMA3CC_DMAQNUM_E7_MASK (0x70000000u)
#define CSL_EDMA3CC_DMAQNUM_E7_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_DMAQNUM_E7_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E6_MASK (0x07000000u)
#define CSL_EDMA3CC_DMAQNUM_E6_SHIFT (0x00000018u)
#define CSL_EDMA3CC_DMAQNUM_E6_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E5_MASK (0x00700000u)
#define CSL_EDMA3CC_DMAQNUM_E5_SHIFT (0x00000014u)
#define CSL_EDMA3CC_DMAQNUM_E5_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E4_MASK (0x00070000u)
#define CSL_EDMA3CC_DMAQNUM_E4_SHIFT (0x00000010u)
#define CSL_EDMA3CC_DMAQNUM_E4_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E3_MASK (0x00007000u)
#define CSL_EDMA3CC_DMAQNUM_E3_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_DMAQNUM_E3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E2_MASK (0x00000700u)
#define CSL_EDMA3CC_DMAQNUM_E2_SHIFT (0x00000008u)
#define CSL_EDMA3CC_DMAQNUM_E2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E1_MASK (0x00000070u)
#define CSL_EDMA3CC_DMAQNUM_E1_SHIFT (0x00000004u)
#define CSL_EDMA3CC_DMAQNUM_E1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E0_MASK (0x00000007u)
#define CSL_EDMA3CC_DMAQNUM_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_RESETVAL (0x00000000u)
/* QDMAQNUM */
#define CSL_EDMA3CC_QDMAQNUM_E3_MASK (0x00007000u)
#define CSL_EDMA3CC_QDMAQNUM_E3_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_QDMAQNUM_E3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QDMAQNUM_E2_MASK (0x00000700u)
#define CSL_EDMA3CC_QDMAQNUM_E2_SHIFT (0x00000008u)
#define CSL_EDMA3CC_QDMAQNUM_E2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QDMAQNUM_E1_MASK (0x00000070u)
#define CSL_EDMA3CC_QDMAQNUM_E1_SHIFT (0x00000004u)
#define CSL_EDMA3CC_QDMAQNUM_E1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QDMAQNUM_E0_MASK (0x00000007u)
#define CSL_EDMA3CC_QDMAQNUM_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QDMAQNUM_E0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QDMAQNUM_RESETVAL (0x00000000u)
/* QUEPRI */
#define CSL_EDMA3CC_QUEPRI_PRIQ3_MASK (0x00007000u)
#define CSL_EDMA3CC_QUEPRI_PRIQ3_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_QUEPRI_PRIQ3_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QUEPRI_PRIQ2_MASK (0x00000700u)
#define CSL_EDMA3CC_QUEPRI_PRIQ2_SHIFT (0x00000008u)
#define CSL_EDMA3CC_QUEPRI_PRIQ2_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QUEPRI_PRIQ1_MASK (0x00000070u)
#define CSL_EDMA3CC_QUEPRI_PRIQ1_SHIFT (0x00000004u)
#define CSL_EDMA3CC_QUEPRI_PRIQ1_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QUEPRI_PRIQ0_MASK (0x00000007u)
#define CSL_EDMA3CC_QUEPRI_PRIQ0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_QUEPRI_PRIQ0_RESETVAL (0x00000000u)
#define CSL_EDMA3CC_QUEPRI_RESETVAL (0x00000000u)
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