cslr_pci.h

Dm6455 driver,magbe useful to you!

#define CSL_PCI_PCIBARMIR_RESETVAL       (0x00000008u)

/* PCIMCFGDAT */

#define CSL_PCI_PCIMCFGDAT_DATA_MASK     (0xFFFFFFFFu)
#define CSL_PCI_PCIMCFGDAT_DATA_SHIFT    (0x00000000u)
#define CSL_PCI_PCIMCFGDAT_DATA_RESETVAL (0x00000000u)

#define CSL_PCI_PCIMCFGDAT_RESETVAL      (0x00000000u)

/* PCIMCFGADR */

#define CSL_PCI_PCIMCFGADR_ADDR_MASK     (0xFFFFFFFFu)
#define CSL_PCI_PCIMCFGADR_ADDR_SHIFT    (0x00000000u)
#define CSL_PCI_PCIMCFGADR_ADDR_RESETVAL (0x00000000u)

#define CSL_PCI_PCIMCFGADR_RESETVAL      (0x00000000u)

/* PCIMCFGCMD */

#define CSL_PCI_PCIMCFGCMD_READY_MASK    (0x80000000u)
#define CSL_PCI_PCIMCFGCMD_READY_SHIFT   (0x0000001Fu)
#define CSL_PCI_PCIMCFGCMD_READY_RESETVAL (0x00000001u)

#define CSL_PCI_PCIMCFGCMD_BYTE_EN_MASK  (0x000000F0u)
#define CSL_PCI_PCIMCFGCMD_BYTE_EN_SHIFT (0x00000004u)
#define CSL_PCI_PCIMCFGCMD_BYTE_EN_RESETVAL (0x00000000u)

#define CSL_PCI_PCIMCFGCMD_TYPE_MASK     (0x00000004u)
#define CSL_PCI_PCIMCFGCMD_TYPE_SHIFT    (0x00000002u)
#define CSL_PCI_PCIMCFGCMD_TYPE_RESETVAL (0x00000000u)

/*----TYPE Tokens----*/
#define CSL_PCI_PCIMCFGCMD_TYPE_CONFIG_SPACE (0x00000000u)
#define CSL_PCI_PCIMCFGCMD_TYPE_IO_SPACE (0x00000001u)

#define CSL_PCI_PCIMCFGCMD_RD_WR_MASK    (0x00000001u)
#define CSL_PCI_PCIMCFGCMD_RD_WR_SHIFT   (0x00000000u)
#define CSL_PCI_PCIMCFGCMD_RD_WR_RESETVAL (0x00000000u)

/*----RD_WR Tokens----*/
#define CSL_PCI_PCIMCFGCMD_RD_WR_WRITE   (0x00000000u)
#define CSL_PCI_PCIMCFGCMD_RD_WR_READ    (0x00000001u)

#define CSL_PCI_PCIMCFGCMD_RESETVAL      (0x80000000u)

/* PCIMSTCFG */

#define CSL_PCI_PCIMSTCFG_CFG_FLUSH_IF_NOT_ENABLED_MASK (0x00000400u)
#define CSL_PCI_PCIMSTCFG_CFG_FLUSH_IF_NOT_ENABLED_SHIFT (0x0000000Au)
#define CSL_PCI_PCIMSTCFG_CFG_FLUSH_IF_NOT_ENABLED_RESETVAL (0x00000000u)

#define CSL_PCI_PCIMSTCFG_IO_FLUSH_IF_NOT_ENABLED_MASK (0x00000200u)
#define CSL_PCI_PCIMSTCFG_IO_FLUSH_IF_NOT_ENABLED_SHIFT (0x00000009u)
#define CSL_PCI_PCIMSTCFG_IO_FLUSH_IF_NOT_ENABLED_RESETVAL (0x00000000u)

#define CSL_PCI_PCIMSTCFG_MEM_FLUSH_IF_NOT_ENABLED_MASK (0x00000100u)
#define CSL_PCI_PCIMSTCFG_MEM_FLUSH_IF_NOT_ENABLED_SHIFT (0x00000008u)
#define CSL_PCI_PCIMSTCFG_MEM_FLUSH_IF_NOT_ENABLED_RESETVAL (0x00000000u)

#define CSL_PCI_PCIMSTCFG_SW_MEM_RD_MULT_EN_MASK (0x00000004u)
#define CSL_PCI_PCIMSTCFG_SW_MEM_RD_MULT_EN_SHIFT (0x00000002u)
#define CSL_PCI_PCIMSTCFG_SW_MEM_RD_MULT_EN_RESETVAL (0x00000001u)

#define CSL_PCI_PCIMSTCFG_SW_MEM_RD_LINE_EN_MASK (0x00000002u)
#define CSL_PCI_PCIMSTCFG_SW_MEM_RD_LINE_EN_SHIFT (0x00000001u)
#define CSL_PCI_PCIMSTCFG_SW_MEM_RD_LINE_EN_RESETVAL (0x00000001u)

#define CSL_PCI_PCIMSTCFG_SW_MEM_WRINV_EN_MASK (0x00000001u)
#define CSL_PCI_PCIMSTCFG_SW_MEM_WRINV_EN_SHIFT (0x00000000u)
#define CSL_PCI_PCIMSTCFG_SW_MEM_WRINV_EN_RESETVAL (0x00000001u)

#define CSL_PCI_PCIMSTCFG_RESETVAL       (0x00000007u)

/* PCIADDSUB */

#define CSL_PCI_PCIADDSUB_ADD_SUBS_MASK  (0xFF800000u)
#define CSL_PCI_PCIADDSUB_ADD_SUBS_SHIFT (0x00000017u)
#define CSL_PCI_PCIADDSUB_ADD_SUBS_RESETVAL (0x00000000u)

#define CSL_PCI_PCIADDSUB_RESETVAL       (0x00000000u)

/* PCIVENDEVPRG */

#define CSL_PCI_PCIVENDEVPRG_VENDOR_DEVICE_ID_PROG_MASK (0xFFFFFFFFu)
#define CSL_PCI_PCIVENDEVPRG_VENDOR_DEVICE_ID_PROG_SHIFT (0x00000000u)
#define CSL_PCI_PCIVENDEVPRG_VENDOR_DEVICE_ID_PROG_RESETVAL (0xB000104Cu)

#define CSL_PCI_PCIVENDEVPRG_RESETVAL    (0xB000104Cu)

/* PCICMDSTATPRG */

#define CSL_PCI_PCICMDSTATPRG_66MHZ_CAP_MASK (0x00000002u)
#define CSL_PCI_PCICMDSTATPRG_66MHZ_CAP_SHIFT (0x00000001u)
#define CSL_PCI_PCICMDSTATPRG_66MHZ_CAP_RESETVAL (0x00000000u)

#define CSL_PCI_PCICMDSTATPRG_CAP_LIST_MASK (0x00000001u)
#define CSL_PCI_PCICMDSTATPRG_CAP_LIST_SHIFT (0x00000000u)
#define CSL_PCI_PCICMDSTATPRG_CAP_LIST_RESETVAL (0x00000000u)

#define CSL_PCI_PCICMDSTATPRG_RESETVAL   (0x00000000u)

/* PCICLREVPRG */

#define CSL_PCI_PCICLREVPRG_CLASS_CODE_REV_ID_PROG_MASK (0xFFFFFFFFu)
#define CSL_PCI_PCICLREVPRG_CLASS_CODE_REV_ID_PROG_SHIFT (0x00000000u)
#define CSL_PCI_PCICLREVPRG_CLASS_CODE_REV_ID_PROG_RESETVAL (0x00000001u)

#define CSL_PCI_PCICLREVPRG_RESETVAL     (0x00000001u)

/* PCISUBIDPRG */

#define CSL_PCI_PCISUBIDPRG_SUBSYS_VENDOR_ID_SUBSYS_ID_PROG_MASK (0xFFFFFFFFu)
#define CSL_PCI_PCISUBIDPRG_SUBSYS_VENDOR_ID_SUBSYS_ID_PROG_SHIFT (0x00000000u)
#define CSL_PCI_PCISUBIDPRG_SUBSYS_VENDOR_ID_SUBSYS_ID_PROG_RESETVAL (0x00000000u)

#define CSL_PCI_PCISUBIDPRG_RESETVAL     (0x00000000u)

/* PCIMAXLGPRG */

#define CSL_PCI_PCIMAXLGPRG_MAX_LAT_MIN_GRANT_PROG_MASK (0x0000FFFFu)
#define CSL_PCI_PCIMAXLGPRG_MAX_LAT_MIN_GRANT_PROG_SHIFT (0x00000000u)
#define CSL_PCI_PCIMAXLGPRG_MAX_LAT_MIN_GRANT_PROG_RESETVAL (0x00000000u)

#define CSL_PCI_PCIMAXLGPRG_RESETVAL     (0x00000000u)

/* PCILRSTREG */

#define CSL_PCI_PCILRSTREG_LRESET_MASK    (0x00000001u)
#define CSL_PCI_PCILRSTREG_LRESET_SHIFT   (0x00000000u)
#define CSL_PCI_PCILRSTREG_LRESET_RESETVAL (0x00000000u)

#define CSL_PCI_PCILRSTREG_RESETVAL       (0x00000000u)

/* PCICFGDONE */

#define CSL_PCI_PCICFGDONE_CONFIG_DONE_MASK (0x00000001u)
#define CSL_PCI_PCICFGDONE_CONFIG_DONE_SHIFT (0x00000000u)
#define CSL_PCI_PCICFGDONE_CONFIG_DONE_RESETVAL (0x00000000u)

#define CSL_PCI_PCICFGDONE_RESETVAL      (0x00000000u)

/* PCIBAR0MPRG */

#define CSL_PCI_PCIBAR0MPRG_MASK_MASK    (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR0MPRG_MASK_SHIFT   (0x00000000u)
#define CSL_PCI_PCIBAR0MPRG_MASK_RESETVAL (0x0FFC0000u)

#define CSL_PCI_PCIBAR0MPRG_RESETVAL     (0x0FFC0000u)

/* PCIBAR1MPRG */

#define CSL_PCI_PCIBAR1MPRG_MASK_MASK    (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR1MPRG_MASK_SHIFT   (0x00000000u)
#define CSL_PCI_PCIBAR1MPRG_MASK_RESETVAL (0x0FF80000u)

#define CSL_PCI_PCIBAR1MPRG_RESETVAL     (0x0FF80000u)

/* PCIBAR2MPRG */

#define CSL_PCI_PCIBAR2MPRG_MASK_MASK    (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR2MPRG_MASK_SHIFT   (0x00000000u)
#define CSL_PCI_PCIBAR2MPRG_MASK_RESETVAL (0x0FFFFFFFu)

#define CSL_PCI_PCIBAR2MPRG_RESETVAL     (0x0FFFFFFFu)

/* PCIBAR3MPRG */

#define CSL_PCI_PCIBAR3MPRG_MASK_MASK    (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR3MPRG_MASK_SHIFT   (0x00000000u)
#define CSL_PCI_PCIBAR3MPRG_MASK_RESETVAL (0x00000000u)

#define CSL_PCI_PCIBAR3MPRG_RESETVAL     (0x00000000u)

/* PCIBAR4MPRG */

#define CSL_PCI_PCIBAR4MPRG_MASK_MASK    (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR4MPRG_MASK_SHIFT   (0x00000000u)
#define CSL_PCI_PCIBAR4MPRG_MASK_RESETVAL (0x00000000u)

#define CSL_PCI_PCIBAR4MPRG_RESETVAL     (0x00000000u)

/* PCIBAR5MPRG */

#define CSL_PCI_PCIBAR5MPRG_MASK_MASK    (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR5MPRG_MASK_SHIFT   (0x00000000u)
#define CSL_PCI_PCIBAR5MPRG_MASK_RESETVAL (0x00000000u)

#define CSL_PCI_PCIBAR5MPRG_RESETVAL     (0x00000000u)

/* PCIBAR0PRG */

#define CSL_PCI_PCIBAR0PRG_PREFETCH_MASK (0x00000001u)
#define CSL_PCI_PCIBAR0PRG_PREFETCH_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR0PRG_PREFETCH_RESETVAL (0x00000001u)

#define CSL_PCI_PCIBAR0PRG_RESETVAL      (0x00000001u)

/* PCIBAR1PRG */

#define CSL_PCI_PCIBAR1PRG_PREFETCH_MASK (0x00000001u)
#define CSL_PCI_PCIBAR1PRG_PREFETCH_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR1PRG_PREFETCH_RESETVAL (0x00000000u)

#define CSL_PCI_PCIBAR1PRG_RESETVAL      (0x00000000u)

/* PCIBAR2PRG */

#define CSL_PCI_PCIBAR2PRG_PREFETCH_MASK (0x00000001u)
#define CSL_PCI_PCIBAR2PRG_PREFETCH_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR2PRG_PREFETCH_RESETVAL (0x00000000u)

#define CSL_PCI_PCIBAR2PRG_RESETVAL      (0x00000000u)

/* PCIBAR3PRG */

#define CSL_PCI_PCIBAR3PRG_PREFETCH_MASK (0x00000001u)
#define CSL_PCI_PCIBAR3PRG_PREFETCH_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR3PRG_PREFETCH_RESETVAL (0x00000000u)

#define CSL_PCI_PCIBAR3PRG_RESETVAL      (0x00000000u)

/* PCIBAR4PRG */

#define CSL_PCI_PCIBAR4PRG_PREFETCH_MASK (0x00000001u)
#define CSL_PCI_PCIBAR4PRG_PREFETCH_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR4PRG_PREFETCH_RESETVAL (0x00000000u)

#define CSL_PCI_PCIBAR4PRG_RESETVAL      (0x00000000u)

/* PCIBAR5PRG */

#define CSL_PCI_PCIBAR5PRG_PREFETCH_MASK (0x00000001u)
#define CSL_PCI_PCIBAR5PRG_PREFETCH_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR5PRG_PREFETCH_RESETVAL (0x00000000u)

#define CSL_PCI_PCIBAR5PRG_RESETVAL      (0x00000000u)

/* PCIBAR0TRLPRG */

#define CSL_PCI_PCIBAR0TRLPRG_TRANS_ADDR_MASK (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR0TRLPRG_TRANS_ADDR_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR0TRLPRG_TRANS_ADDR_RESETVAL (0x00080000u)

#define CSL_PCI_PCIBAR0TRLPRG_RESETVAL   (0x00080000u)

/* PCIBAR1TRLPRG */

#define CSL_PCI_PCIBAR1TRLPRG_TRANS_ADDR_MASK (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR1TRLPRG_TRANS_ADDR_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR1TRLPRG_TRANS_ADDR_RESETVAL (0x00180000u)

#define CSL_PCI_PCIBAR1TRLPRG_RESETVAL   (0x00180000u)

/* PCIBAR2TRLPRG */

#define CSL_PCI_PCIBAR2TRLPRG_TRANS_ADDR_MASK (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR2TRLPRG_TRANS_ADDR_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR2TRLPRG_TRANS_ADDR_RESETVAL (0x00280000u)

#define CSL_PCI_PCIBAR2TRLPRG_RESETVAL   (0x00280000u)

/* PCIBAR3TRLPRG */

#define CSL_PCI_PCIBAR3TRLPRG_TRANS_ADDR_MASK (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR3TRLPRG_TRANS_ADDR_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR3TRLPRG_TRANS_ADDR_RESETVAL (0x08000000u)

#define CSL_PCI_PCIBAR3TRLPRG_RESETVAL   (0x08000000u)

/* PCIBAR4TRLPRG */

#define CSL_PCI_PCIBAR4TRLPRG_TRANS_ADDR_MASK (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR4TRLPRG_TRANS_ADDR_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR4TRLPRG_TRANS_ADDR_RESETVAL (0x0A000000u)

#define CSL_PCI_PCIBAR4TRLPRG_RESETVAL   (0x0A000000u)

/* PCIBAR5TRLPRG */

#define CSL_PCI_PCIBAR5TRLPRG_TRANS_ADDR_MASK (0x0FFFFFFFu)
#define CSL_PCI_PCIBAR5TRLPRG_TRANS_ADDR_SHIFT (0x00000000u)
#define CSL_PCI_PCIBAR5TRLPRG_TRANS_ADDR_RESETVAL (0x0E000000u)

#define CSL_PCI_PCIBAR5TRLPRG_RESETVAL   (0x0E000000u)

/* PCIBASENPRG */

#define CSL_PCI_PCIBASENPRG_BASE_EN_MASK (0x0000003Fu)
#define CSL_PCI_PCIBASENPRG_BASE_EN_SHIFT (0x00000000u)
#define CSL_PCI_PCIBASENPRG_BASE_EN_RESETVAL (0x0000003Fu)

#define CSL_PCI_PCIBASENPRG_RESETVAL     (0x0000003Fu)

#endif