cslr_pci.h

Dm6455 driver,magbe useful to you!

#define CSL_PCI_PCICSRMIR_FAST_BTOB_EN_MASK (0x00000200u)
#define CSL_PCI_PCICSRMIR_FAST_BTOB_EN_SHIFT (0x00000009u)
#define CSL_PCI_PCICSRMIR_FAST_BTOB_EN_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_SERR_N_EN_MASK (0x00000100u)
#define CSL_PCI_PCICSRMIR_SERR_N_EN_SHIFT (0x00000008u)
#define CSL_PCI_PCICSRMIR_SERR_N_EN_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_PAR_ERR_RES_MASK (0x00000040u)
#define CSL_PCI_PCICSRMIR_PAR_ERR_RES_SHIFT (0x00000006u)
#define CSL_PCI_PCICSRMIR_PAR_ERR_RES_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_VGA_PAL_SNP_MASK (0x00000020u)
#define CSL_PCI_PCICSRMIR_VGA_PAL_SNP_SHIFT (0x00000005u)
#define CSL_PCI_PCICSRMIR_VGA_PAL_SNP_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_MEM_WRINV_EN_MASK (0x00000010u)
#define CSL_PCI_PCICSRMIR_MEM_WRINV_EN_SHIFT (0x00000004u)
#define CSL_PCI_PCICSRMIR_MEM_WRINV_EN_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_SP_CYCL_MASK   (0x00000008u)
#define CSL_PCI_PCICSRMIR_SP_CYCL_SHIFT  (0x00000003u)
#define CSL_PCI_PCICSRMIR_SP_CYCL_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_BUS_MS_MASK    (0x00000004u)
#define CSL_PCI_PCICSRMIR_BUS_MS_SHIFT   (0x00000002u)
#define CSL_PCI_PCICSRMIR_BUS_MS_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_MEM_SP_MASK    (0x00000002u)
#define CSL_PCI_PCICSRMIR_MEM_SP_SHIFT   (0x00000001u)
#define CSL_PCI_PCICSRMIR_MEM_SP_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_IO_SP_MASK     (0x00000001u)
#define CSL_PCI_PCICSRMIR_IO_SP_SHIFT    (0x00000000u)
#define CSL_PCI_PCICSRMIR_IO_SP_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_RESETVAL       (0x02000000u)

/* PCICLREVMIR */

#define CSL_PCI_PCICLREVMIR_CL_CODE_MASK (0xFFFFFF00u)
#define CSL_PCI_PCICLREVMIR_CL_CODE_SHIFT (0x00000008u)
#define CSL_PCI_PCICLREVMIR_CL_CODE_RESETVAL (0x00000000u)

#define CSL_PCI_PCICLREVMIR_REV_ID_MASK  (0x000000FFu)
#define CSL_PCI_PCICLREVMIR_REV_ID_SHIFT (0x00000000u)
#define CSL_PCI_PCICLREVMIR_REV_ID_RESETVAL (0x00000001u)

#define CSL_PCI_PCICLREVMIR_RESETVAL     (0x00000001u)

/* PCICLINEMIR */

#define CSL_PCI_PCICLINEMIR_BIST_MASK    (0xFF000000u)
#define CSL_PCI_PCICLINEMIR_BIST_SHIFT   (0x00000018u)
#define CSL_PCI_PCICLINEMIR_BIST_RESETVAL (0x00000000u)

#define CSL_PCI_PCICLINEMIR_HDR_TYPE_MASK (0x00FF0000u)
#define CSL_PCI_PCICLINEMIR_HDR_TYPE_SHIFT (0x00000010u)
#define CSL_PCI_PCICLINEMIR_HDR_TYPE_RESETVAL (0x00000000u)

#define CSL_PCI_PCICLINEMIR_LAT_TMR_MASK (0x0000FF00u)
#define CSL_PCI_PCICLINEMIR_LAT_TMR_SHIFT (0x00000008u)
#define CSL_PCI_PCICLINEMIR_LAT_TMR_RESETVAL (0x00000000u)

#define CSL_PCI_PCICLINEMIR_CACHELN_SIZ_MASK (0x000000FFu)
#define CSL_PCI_PCICLINEMIR_CACHELN_SIZ_SHIFT (0x00000000u)
#define CSL_PCI_PCICLINEMIR_CACHELN_SIZ_RESETVAL (0x00000000u)

#define CSL_PCI_PCICLINEMIR_RESETVAL     (0x00000000u)

/* PCIBAR0MSK */

#define CSL_PCI_PCIBAR0MSK_ADDRMASK_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR0MSK_ADDRMASK_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR0MSK_ADDRMASK_RESETVAL (0x0FF80000u)

#define CSL_PCI_PCIBAR0MSK_PREFETCH_EN_MASK (0x00000008u)
#define CSL_PCI_PCIBAR0MSK_PREFETCH_EN_SHIFT (0x00000003u)
#define CSL_PCI_PCIBAR0MSK_PREFETCH_EN_RESETVAL (0x00000001u)

#define CSL_PCI_PCIBAR0MSK_RESETVAL      (0xFF800008u)

/* PCIBAR1MSK */

#define CSL_PCI_PCIBAR1MSK_ADDRMASK_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR1MSK_ADDRMASK_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR1MSK_ADDRMASK_RESETVAL (0x0FFC0000u)

#define CSL_PCI_PCIBAR1MSK_PREFETCH_EN_MASK (0x00000008u)
#define CSL_PCI_PCIBAR1MSK_PREFETCH_EN_SHIFT (0x00000003u)
#define CSL_PCI_PCIBAR1MSK_PREFETCH_EN_RESETVAL (0x00000001u)

#define CSL_PCI_PCIBAR1MSK_RESETVAL      (0xFFC00008u)

/* PCIBAR2MSK */

#define CSL_PCI_PCIBAR2MSK_ADDRMASK_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR2MSK_ADDRMASK_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR2MSK_ADDRMASK_RESETVAL (0x0FF80000u)

#define CSL_PCI_PCIBAR2MSK_PREFETCH_EN_MASK (0x00000008u)
#define CSL_PCI_PCIBAR2MSK_PREFETCH_EN_SHIFT (0x00000003u)
#define CSL_PCI_PCIBAR2MSK_PREFETCH_EN_RESETVAL (0x00000001u)

#define CSL_PCI_PCIBAR2MSK_RESETVAL      (0xFF800008u)

/* PCIBAR3MSK */

#define CSL_PCI_PCIBAR3MSK_ADDRMASK_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR3MSK_ADDRMASK_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR3MSK_ADDRMASK_RESETVAL (0x0FF80000u)

#define CSL_PCI_PCIBAR3MSK_PREFETCH_EN_MASK (0x00000008u)
#define CSL_PCI_PCIBAR3MSK_PREFETCH_EN_SHIFT (0x00000003u)
#define CSL_PCI_PCIBAR3MSK_PREFETCH_EN_RESETVAL (0x00000001u)

#define CSL_PCI_PCIBAR3MSK_RESETVAL      (0xFF800008u)

/* PCIBAR4MSK */

#define CSL_PCI_PCIBAR4MSK_ADDRMASK_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR4MSK_ADDRMASK_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR4MSK_ADDRMASK_RESETVAL (0x0FF80000u)

#define CSL_PCI_PCIBAR4MSK_PREFETCH_EN_MASK (0x00000008u)
#define CSL_PCI_PCIBAR4MSK_PREFETCH_EN_SHIFT (0x00000003u)
#define CSL_PCI_PCIBAR4MSK_PREFETCH_EN_RESETVAL (0x00000001u)

#define CSL_PCI_PCIBAR4MSK_RESETVAL      (0xFF800008u)

/* PCIBAR5MSK */

#define CSL_PCI_PCIBAR5MSK_ADDRMASK_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR5MSK_ADDRMASK_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR5MSK_ADDRMASK_RESETVAL (0x0FF80000u)

#define CSL_PCI_PCIBAR5MSK_PREFETCH_EN_MASK (0x00000008u)
#define CSL_PCI_PCIBAR5MSK_PREFETCH_EN_SHIFT (0x00000003u)
#define CSL_PCI_PCIBAR5MSK_PREFETCH_EN_RESETVAL (0x00000001u)

#define CSL_PCI_PCIBAR5MSK_RESETVAL      (0xFF800008u)

/* PCISUBIDMIR */

#define CSL_PCI_PCISUBIDMIR_SUBSYS_ID_MASK (0xFFFF0000u)
#define CSL_PCI_PCISUBIDMIR_SUBSYS_ID_SHIFT (0x00000010u)
#define CSL_PCI_PCISUBIDMIR_SUBSYS_ID_RESETVAL (0x00000000u)

#define CSL_PCI_PCISUBIDMIR_SUBSYS_VEN_ID_MASK (0x0000FFFFu)
#define CSL_PCI_PCISUBIDMIR_SUBSYS_VEN_ID_SHIFT (0x00000000u)
#define CSL_PCI_PCISUBIDMIR_SUBSYS_VEN_ID_RESETVAL (0x00000000u)

#define CSL_PCI_PCISUBIDMIR_RESETVAL     (0x00000000u)

/* PCICPBPTRMIR */

#define CSL_PCI_PCICPBPTRMIR_CAP_MASK    (0x000000FFu)
#define CSL_PCI_PCICPBPTRMIR_CAP_SHIFT   (0x00000000u)
#define CSL_PCI_PCICPBPTRMIR_CAP_RESETVAL (0x00000040u)

#define CSL_PCI_PCICPBPTRMIR_RESETVAL    (0x00000040u)

/* PCILGINTMIR */

#define CSL_PCI_PCILGINTMIR_MAX_LAT_MASK (0xFF000000u)
#define CSL_PCI_PCILGINTMIR_MAX_LAT_SHIFT (0x00000018u)
#define CSL_PCI_PCILGINTMIR_MAX_LAT_RESETVAL (0x00000000u)

#define CSL_PCI_PCILGINTMIR_MIN_GRNT_MASK (0x00FF0000u)
#define CSL_PCI_PCILGINTMIR_MIN_GRNT_SHIFT (0x00000010u)
#define CSL_PCI_PCILGINTMIR_MIN_GRNT_RESETVAL (0x00000000u)

#define CSL_PCI_PCILGINTMIR_INT_PIN_MASK (0x0000FF00u)
#define CSL_PCI_PCILGINTMIR_INT_PIN_SHIFT (0x00000008u)
#define CSL_PCI_PCILGINTMIR_INT_PIN_RESETVAL (0x00000001u)

#define CSL_PCI_PCILGINTMIR_INT_LINE_MASK (0x000000FFu)
#define CSL_PCI_PCILGINTMIR_INT_LINE_SHIFT (0x00000000u)
#define CSL_PCI_PCILGINTMIR_INT_LINE_RESETVAL (0x00000000u)

#define CSL_PCI_PCILGINTMIR_RESETVAL     (0x00000100u)

/* PCISLVCNTL */

#define CSL_PCI_PCISLVCNTL_BASE5_EN_MASK (0x00200000u)
#define CSL_PCI_PCISLVCNTL_BASE5_EN_SHIFT (0x00000015u)
#define CSL_PCI_PCISLVCNTL_BASE5_EN_RESETVAL (0x00000001u)

#define CSL_PCI_PCISLVCNTL_BASE4_EN_MASK (0x00100000u)
#define CSL_PCI_PCISLVCNTL_BASE4_EN_SHIFT (0x00000014u)
#define CSL_PCI_PCISLVCNTL_BASE4_EN_RESETVAL (0x00000001u)

#define CSL_PCI_PCISLVCNTL_BASE3_EN_MASK (0x00080000u)
#define CSL_PCI_PCISLVCNTL_BASE3_EN_SHIFT (0x00000013u)
#define CSL_PCI_PCISLVCNTL_BASE3_EN_RESETVAL (0x00000001u)

#define CSL_PCI_PCISLVCNTL_BASE2_EN_MASK (0x00040000u)
#define CSL_PCI_PCISLVCNTL_BASE2_EN_SHIFT (0x00000012u)
#define CSL_PCI_PCISLVCNTL_BASE2_EN_RESETVAL (0x00000001u)

#define CSL_PCI_PCISLVCNTL_BASE1_EN_MASK (0x00020000u)
#define CSL_PCI_PCISLVCNTL_BASE1_EN_SHIFT (0x00000011u)
#define CSL_PCI_PCISLVCNTL_BASE1_EN_RESETVAL (0x00000001u)

#define CSL_PCI_PCISLVCNTL_BASE0_EN_MASK (0x00010000u)
#define CSL_PCI_PCISLVCNTL_BASE0_EN_SHIFT (0x00000010u)
#define CSL_PCI_PCISLVCNTL_BASE0_EN_RESETVAL (0x00000001u)

#define CSL_PCI_PCISLVCNTL_FORCE_DEL_READ_MUL_MASK (0x00000010u)
#define CSL_PCI_PCISLVCNTL_FORCE_DEL_READ_MUL_SHIFT (0x00000004u)
#define CSL_PCI_PCISLVCNTL_FORCE_DEL_READ_MUL_RESETVAL (0x00000000u)

#define CSL_PCI_PCISLVCNTL_FORCE_DEL_READ_LN_MASK (0x00000008u)
#define CSL_PCI_PCISLVCNTL_FORCE_DEL_READ_LN_SHIFT (0x00000003u)
#define CSL_PCI_PCISLVCNTL_FORCE_DEL_READ_LN_RESETVAL (0x00000000u)

#define CSL_PCI_PCISLVCNTL_FORCE_DEL_READ_MASK (0x00000004u)
#define CSL_PCI_PCISLVCNTL_FORCE_DEL_READ_SHIFT (0x00000002u)
#define CSL_PCI_PCISLVCNTL_FORCE_DEL_READ_RESETVAL (0x00000000u)

#define CSL_PCI_PCISLVCNTL_DIS_SLV_TOUT_MASK (0x00000002u)
#define CSL_PCI_PCISLVCNTL_DIS_SLV_TOUT_SHIFT (0x00000001u)
#define CSL_PCI_PCISLVCNTL_DIS_SLV_TOUT_RESETVAL (0x00000000u)

#define CSL_PCI_PCISLVCNTL_CFG_DONE_MASK (0x00000001u)
#define CSL_PCI_PCISLVCNTL_CFG_DONE_SHIFT (0x00000000u)
#define CSL_PCI_PCISLVCNTL_CFG_DONE_RESETVAL (0x00000000u)

#define CSL_PCI_PCISLVCNTL_RESETVAL      (0x003F0000u)

/* PCIBAR0TRL */

#define CSL_PCI_PCIBAR0TRL_TRANS_ADDR_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR0TRL_TRANS_ADDR_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR0TRL_TRANS_ADDR_RESETVAL (0x00080000u)

#define CSL_PCI_PCIBAR0TRL_RESETVAL      (0x00800000u)

/* PCIBAR1TRL */

#define CSL_PCI_PCIBAR1TRL_TRANS_ADDR_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR1TRL_TRANS_ADDR_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR1TRL_TRANS_ADDR_RESETVAL (0x00180000u)

#define CSL_PCI_PCIBAR1TRL_RESETVAL      (0x01800000u)

/* PCIBAR2TRL */

#define CSL_PCI_PCIBAR2TRL_TRANS_ADDR_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR2TRL_TRANS_ADDR_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR2TRL_TRANS_ADDR_RESETVAL (0x00280000u)

#define CSL_PCI_PCIBAR2TRL_RESETVAL      (0x02800000u)

/* PCIBAR3TRL */

#define CSL_PCI_PCIBAR3TRL_TRANS_ADDR_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR3TRL_TRANS_ADDR_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR3TRL_TRANS_ADDR_RESETVAL (0x08000000u)

#define CSL_PCI_PCIBAR3TRL_RESETVAL      (0x80000000u)

/* PCIBAR4TRL */

#define CSL_PCI_PCIBAR4TRL_TRANS_ADDR_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR4TRL_TRANS_ADDR_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR4TRL_TRANS_ADDR_RESETVAL (0x0A000000u)

#define CSL_PCI_PCIBAR4TRL_RESETVAL      (0xA0000000u)

/* PCIBAR5TRL */

#define CSL_PCI_PCIBAR5TRL_TRANS_ADDR_MASK (0xFFFFFFF0u)
#define CSL_PCI_PCIBAR5TRL_TRANS_ADDR_SHIFT (0x00000004u)
#define CSL_PCI_PCIBAR5TRL_TRANS_ADDR_RESETVAL (0x0E000000u)

#define CSL_PCI_PCIBAR5TRL_RESETVAL      (0xE0000000u)

/* PCIBARMIR */

#define CSL_PCI_PCIBARMIR_ADDR_MASK      (0xFFFFFFF0u)
#define CSL_PCI_PCIBARMIR_ADDR_SHIFT     (0x00000004u)
#define CSL_PCI_PCIBARMIR_ADDR_RESETVAL  (0x00000000u)

#define CSL_PCI_PCIBARMIR_PREFETCH_MASK  (0x00000008u)
#define CSL_PCI_PCIBARMIR_PREFETCH_SHIFT (0x00000003u)
#define CSL_PCI_PCIBARMIR_PREFETCH_RESETVAL (0x00000001u)

#define CSL_PCI_PCIBARMIR_TYPE_MASK      (0x00000006u)
#define CSL_PCI_PCIBARMIR_TYPE_SHIFT     (0x00000001u)
#define CSL_PCI_PCIBARMIR_TYPE_RESETVAL  (0x00000000u)

#define CSL_PCI_PCIBARMIR_IOMEM_SP_IND_MASK (0x00000001u)
#define CSL_PCI_PCIBARMIR_IOMEM_SP_IND_SHIFT (0x00000000u)
#define CSL_PCI_PCIBARMIR_IOMEM_SP_IND_RESETVAL (0x00000000u)