cslr_pci.h

Dm6455 driver,magbe useful to you!

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */
/** ============================================================================
 *   @file  cslr_pci.h
 *
 *   @path  $(CSLPATH)\inc
 *
 *   @desc  This file contains the Register Descriptions for PCI
 */
#ifndef _CSLR_PCI_H_
#define _CSLR_PCI_H_

#include <cslr.h>
#include <tistdtypes.h>

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint8 RSVD0[16];
    volatile Uint32 PCISTATSET;
    volatile Uint32 PCISTATCLR;
    volatile Uint8 RSVD1[8];
    volatile Uint32 PCIHINTSET;
    volatile Uint32 PCIHINTCLR;
    volatile Uint8 RSVD2[8];
    volatile Uint32 PCIBINTSET;
    volatile Uint32 PCIBINTCLR;
    volatile Uint8 RSVD3[200];
    volatile Uint32 PCIVENDEVMIR;
    volatile Uint32 PCICSRMIR;
    volatile Uint32 PCICLREVMIR;
    volatile Uint32 PCICLINEMIR;
    volatile Uint32 PCIBAR0MSK;
    volatile Uint32 PCIBAR1MSK;
    volatile Uint32 PCIBAR2MSK;
    volatile Uint32 PCIBAR3MSK;
    volatile Uint32 PCIBAR4MSK;
    volatile Uint32 PCIBAR5MSK;
    volatile Uint8 RSVD4[4];
    volatile Uint32 PCISUBIDMIR;
    volatile Uint8 RSVD5[4];
    volatile Uint32 PCICPBPTRMIR;
    volatile Uint8 RSVD6[4];
    volatile Uint32 PCILGINTMIR;
    volatile Uint8 RSVD7[64];
    volatile Uint32 PCISLVCNTL;
    volatile Uint8 RSVD8[60];
    volatile Uint32 PCIBAR0TRL;
    volatile Uint32 PCIBAR1TRL;
    volatile Uint32 PCIBAR2TRL;
    volatile Uint32 PCIBAR3TRL;
    volatile Uint32 PCIBAR4TRL;
    volatile Uint32 PCIBAR5TRL;
    volatile Uint8 RSVD9[8];
    volatile Uint32 PCIBARMIR[6];
    volatile Uint8 RSVD10[264];
    volatile Uint32 PCIMCFGDAT;
    volatile Uint32 PCIMCFGADR;
    volatile Uint32 PCIMCFGCMD;
    volatile Uint8 RSVD11[4];
    volatile Uint32 PCIMSTCFG;
    volatile Uint32 PCIADDSUB[32];
    volatile Uint32 PCIVENDEVPRG;
    volatile Uint32 PCICMDSTATPRG;
    volatile Uint32 PCICLREVPRG;
    volatile Uint32 PCISUBIDPRG;
    volatile Uint32 PCIMAXLGPRG;
    volatile Uint32 PCILRSTREG;
    volatile Uint32 PCICFGDONE;
    volatile Uint32 PCIBAR0MPRG;
    volatile Uint32 PCIBAR1MPRG;
    volatile Uint32 PCIBAR2MPRG;
    volatile Uint32 PCIBAR3MPRG;
    volatile Uint32 PCIBAR4MPRG;
    volatile Uint32 PCIBAR5MPRG;
    volatile Uint32 PCIBAR0PRG;
    volatile Uint32 PCIBAR1PRG;
    volatile Uint32 PCIBAR2PRG;
    volatile Uint32 PCIBAR3PRG;
    volatile Uint32 PCIBAR4PRG;
    volatile Uint32 PCIBAR5PRG;
    volatile Uint32 PCIBAR0TRLPRG;
    volatile Uint32 PCIBAR1TRLPRG;
    volatile Uint32 PCIBAR2TRLPRG;
    volatile Uint32 PCIBAR3TRLPRG;
    volatile Uint32 PCIBAR4TRLPRG;
    volatile Uint32 PCIBAR5TRLPRG;
    volatile Uint32 PCIBASENPRG;
} CSL_PciRegs;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* PCISTATSET */

#define CSL_PCI_PCISTATSET_DSPINT_MASK   (0x80000000u)
#define CSL_PCI_PCISTATSET_DSPINT_SHIFT  (0x0000001Fu)
#define CSL_PCI_PCISTATSET_DSPINT_RESETVAL (0x00000000u)

#define CSL_PCI_PCISTATSET_PERR_DET_MASK (0x00000040u)
#define CSL_PCI_PCISTATSET_PERR_DET_SHIFT (0x00000006u)
#define CSL_PCI_PCISTATSET_PERR_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCISTATSET_SERR_DET_MASK (0x00000020u)
#define CSL_PCI_PCISTATSET_SERR_DET_SHIFT (0x00000005u)
#define CSL_PCI_PCISTATSET_SERR_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCISTATSET_MS_ABRT_DET_MASK (0x00000004u)
#define CSL_PCI_PCISTATSET_MS_ABRT_DET_SHIFT (0x00000002u)
#define CSL_PCI_PCISTATSET_MS_ABRT_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCISTATSET_TGT_ABRT_DET_MASK (0x00000002u)
#define CSL_PCI_PCISTATSET_TGT_ABRT_DET_SHIFT (0x00000001u)
#define CSL_PCI_PCISTATSET_TGT_ABRT_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCISTATSET_RESETVAL      (0x00000000u)

/* PCISTATCLR */

#define CSL_PCI_PCISTATCLR_DSPINT_MASK   (0x80000000u)
#define CSL_PCI_PCISTATCLR_DSPINT_SHIFT  (0x0000001Fu)
#define CSL_PCI_PCISTATCLR_DSPINT_RESETVAL (0x00000000u)

#define CSL_PCI_PCISTATCLR_PERR_DET_MASK (0x00000040u)
#define CSL_PCI_PCISTATCLR_PERR_DET_SHIFT (0x00000006u)
#define CSL_PCI_PCISTATCLR_PERR_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCISTATCLR_SERR_DET_MASK (0x00000020u)
#define CSL_PCI_PCISTATCLR_SERR_DET_SHIFT (0x00000005u)
#define CSL_PCI_PCISTATCLR_SERR_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCISTATCLR_MS_ABRT_DET_MASK (0x00000004u)
#define CSL_PCI_PCISTATCLR_MS_ABRT_DET_SHIFT (0x00000002u)
#define CSL_PCI_PCISTATCLR_MS_ABRT_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCISTATCLR_TGT_ABRT_DET_MASK (0x00000002u)
#define CSL_PCI_PCISTATCLR_TGT_ABRT_DET_SHIFT (0x00000001u)
#define CSL_PCI_PCISTATCLR_TGT_ABRT_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCISTATCLR_RESETVAL      (0x00000000u)

/* PCIHINTSET */

#define CSL_PCI_PCIHINTSET_PERR_DET_MASK (0x00000040u)
#define CSL_PCI_PCIHINTSET_PERR_DET_SHIFT (0x00000006u)
#define CSL_PCI_PCIHINTSET_PERR_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCIHINTSET_SERR_DET_MASK (0x00000020u)
#define CSL_PCI_PCIHINTSET_SERR_DET_SHIFT (0x00000005u)
#define CSL_PCI_PCIHINTSET_SERR_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCIHINTSET_MS_ABRT_DET_MASK (0x00000004u)
#define CSL_PCI_PCIHINTSET_MS_ABRT_DET_SHIFT (0x00000002u)
#define CSL_PCI_PCIHINTSET_MS_ABRT_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCIHINTSET_TGT_ABRT_DET_MASK (0x00000002u)
#define CSL_PCI_PCIHINTSET_TGT_ABRT_DET_SHIFT (0x00000001u)
#define CSL_PCI_PCIHINTSET_TGT_ABRT_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCIHINTSET_RESETVAL      (0x00000000u)

/* PCIHINTCLR */

#define CSL_PCI_PCIHINTCLR_PERR_DET_MASK (0x00000040u)
#define CSL_PCI_PCIHINTCLR_PERR_DET_SHIFT (0x00000006u)
#define CSL_PCI_PCIHINTCLR_PERR_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCIHINTCLR_SERR_DET_MASK (0x00000020u)
#define CSL_PCI_PCIHINTCLR_SERR_DET_SHIFT (0x00000005u)
#define CSL_PCI_PCIHINTCLR_SERR_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCIHINTCLR_MS_ABRT_DET_MASK (0x00000004u)
#define CSL_PCI_PCIHINTCLR_MS_ABRT_DET_SHIFT (0x00000002u)
#define CSL_PCI_PCIHINTCLR_MS_ABRT_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCIHINTCLR_TGT_ABRT_DET_MASK (0x00000002u)
#define CSL_PCI_PCIHINTCLR_TGT_ABRT_DET_SHIFT (0x00000001u)
#define CSL_PCI_PCIHINTCLR_TGT_ABRT_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCIHINTCLR_RESETVAL      (0x00000000u)

/* PCIBINTSET */

#define CSL_PCI_PCIBINTSET_DSPINT_MASK   (0x80000000u)
#define CSL_PCI_PCIBINTSET_DSPINT_SHIFT  (0x0000001Fu)
#define CSL_PCI_PCIBINTSET_DSPINT_RESETVAL (0x00000000u)

#define CSL_PCI_PCIBINTSET_PERR_DET_MASK (0x00000040u)
#define CSL_PCI_PCIBINTSET_PERR_DET_SHIFT (0x00000006u)
#define CSL_PCI_PCIBINTSET_PERR_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCIBINTSET_SERR_DET_MASK (0x00000020u)
#define CSL_PCI_PCIBINTSET_SERR_DET_SHIFT (0x00000005u)
#define CSL_PCI_PCIBINTSET_SERR_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCIBINTSET_MS_ABRT_DET_MASK (0x00000004u)
#define CSL_PCI_PCIBINTSET_MS_ABRT_DET_SHIFT (0x00000002u)
#define CSL_PCI_PCIBINTSET_MS_ABRT_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCIBINTSET_TGT_ABRT_DET_MASK (0x00000002u)
#define CSL_PCI_PCIBINTSET_TGT_ABRT_DET_SHIFT (0x00000001u)
#define CSL_PCI_PCIBINTSET_TGT_ABRT_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCIBINTSET_RESETVAL      (0x00000000u)

/* PCIBINTCLR */

#define CSL_PCI_PCIBINTCLR_DSPINT_MASK   (0x80000000u)
#define CSL_PCI_PCIBINTCLR_DSPINT_SHIFT  (0x0000001Fu)
#define CSL_PCI_PCIBINTCLR_DSPINT_RESETVAL (0x00000000u)

#define CSL_PCI_PCIBINTCLR_PERR_DET_MASK (0x00000040u)
#define CSL_PCI_PCIBINTCLR_PERR_DET_SHIFT (0x00000006u)
#define CSL_PCI_PCIBINTCLR_PERR_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCIBINTCLR_SERR_DET_MASK (0x00000020u)
#define CSL_PCI_PCIBINTCLR_SERR_DET_SHIFT (0x00000005u)
#define CSL_PCI_PCIBINTCLR_SERR_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCIBINTCLR_MS_ABRT_DET_MASK (0x00000004u)
#define CSL_PCI_PCIBINTCLR_MS_ABRT_DET_SHIFT (0x00000002u)
#define CSL_PCI_PCIBINTCLR_MS_ABRT_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCIBINTCLR_TGT_ABRT_DET_MASK (0x00000002u)
#define CSL_PCI_PCIBINTCLR_TGT_ABRT_DET_SHIFT (0x00000001u)
#define CSL_PCI_PCIBINTCLR_TGT_ABRT_DET_RESETVAL (0x00000000u)

#define CSL_PCI_PCIBINTCLR_RESETVAL      (0x00000000u)

/* PCIVENDEVMIR */

#define CSL_PCI_PCIVENDEVMIR_DEV_ID_MASK (0xFFFF0000u)
#define CSL_PCI_PCIVENDEVMIR_DEV_ID_SHIFT (0x00000010u)
#define CSL_PCI_PCIVENDEVMIR_DEV_ID_RESETVAL (0x0000B000u)

#define CSL_PCI_PCIVENDEVMIR_VEN_ID_MASK (0x0000FFFFu)
#define CSL_PCI_PCIVENDEVMIR_VEN_ID_SHIFT (0x00000000u)
#define CSL_PCI_PCIVENDEVMIR_VEN_ID_RESETVAL (0x0000104Cu)

#define CSL_PCI_PCIVENDEVMIR_RESETVAL    (0xB000104Cu)

/* PCICSRMIR */

#define CSL_PCI_PCICSRMIR_DET_PAR_ERR_MASK (0x80000000u)
#define CSL_PCI_PCICSRMIR_DET_PAR_ERR_SHIFT (0x0000001Fu)
#define CSL_PCI_PCICSRMIR_DET_PAR_ERR_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_SIG_SYS_ERR_MASK (0x40000000u)
#define CSL_PCI_PCICSRMIR_SIG_SYS_ERR_SHIFT (0x0000001Eu)
#define CSL_PCI_PCICSRMIR_SIG_SYS_ERR_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_RCV_MS_ABRT_MASK (0x20000000u)
#define CSL_PCI_PCICSRMIR_RCV_MS_ABRT_SHIFT (0x0000001Du)
#define CSL_PCI_PCICSRMIR_RCV_MS_ABRT_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_RCV_TGT_ABRT_MASK (0x10000000u)
#define CSL_PCI_PCICSRMIR_RCV_TGT_ABRT_SHIFT (0x0000001Cu)
#define CSL_PCI_PCICSRMIR_RCV_TGT_ABRT_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_SIG_TGT_ABRT_MASK (0x08000000u)
#define CSL_PCI_PCICSRMIR_SIG_TGT_ABRT_SHIFT (0x0000001Bu)
#define CSL_PCI_PCICSRMIR_SIG_TGT_ABRT_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_DEVSEL_TIM_MASK (0x06000000u)
#define CSL_PCI_PCICSRMIR_DEVSEL_TIM_SHIFT (0x00000019u)
#define CSL_PCI_PCICSRMIR_DEVSEL_TIM_RESETVAL (0x00000001u)

#define CSL_PCI_PCICSRMIR_MS_DPAR_REP_MASK (0x01000000u)
#define CSL_PCI_PCICSRMIR_MS_DPAR_REP_SHIFT (0x00000018u)
#define CSL_PCI_PCICSRMIR_MS_DPAR_REP_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_FAST_BTOB_CAP_MASK (0x00800000u)
#define CSL_PCI_PCICSRMIR_FAST_BTOB_CAP_SHIFT (0x00000017u)
#define CSL_PCI_PCICSRMIR_FAST_BTOB_CAP_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_66MHZ_CAP_MASK (0x00200000u)
#define CSL_PCI_PCICSRMIR_66MHZ_CAP_SHIFT (0x00000015u)
#define CSL_PCI_PCICSRMIR_66MHZ_CAP_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_CAP_LIST_IMPL_MASK (0x00100000u)
#define CSL_PCI_PCICSRMIR_CAP_LIST_IMPL_SHIFT (0x00000014u)
#define CSL_PCI_PCICSRMIR_CAP_LIST_IMPL_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_INT_STAT_MASK  (0x00080000u)
#define CSL_PCI_PCICSRMIR_INT_STAT_SHIFT (0x00000013u)
#define CSL_PCI_PCICSRMIR_INT_STAT_RESETVAL (0x00000000u)

#define CSL_PCI_PCICSRMIR_INT_DIS_MASK   (0x00000400u)
#define CSL_PCI_PCICSRMIR_INT_DIS_SHIFT  (0x0000000Au)
#define CSL_PCI_PCICSRMIR_INT_DIS_RESETVAL (0x00000000u)