cslr_gpio.h

Dm6455 driver,magbe useful to you!

#define CSL_GPIO_IN_DATA_IN14_MASK       (0x00004000u)
#define CSL_GPIO_IN_DATA_IN14_SHIFT      (0x0000000Eu)
#define CSL_GPIO_IN_DATA_IN14_RESETVAL   (0x00000000u)

#define CSL_GPIO_IN_DATA_IN13_MASK       (0x00002000u)
#define CSL_GPIO_IN_DATA_IN13_SHIFT      (0x0000000Du)
#define CSL_GPIO_IN_DATA_IN13_RESETVAL   (0x00000000u)

#define CSL_GPIO_IN_DATA_IN12_MASK       (0x00001000u)
#define CSL_GPIO_IN_DATA_IN12_SHIFT      (0x0000000Cu)
#define CSL_GPIO_IN_DATA_IN12_RESETVAL   (0x00000000u)

#define CSL_GPIO_IN_DATA_IN11_MASK       (0x00000800u)
#define CSL_GPIO_IN_DATA_IN11_SHIFT      (0x0000000Bu)
#define CSL_GPIO_IN_DATA_IN11_RESETVAL   (0x00000000u)

#define CSL_GPIO_IN_DATA_IN10_MASK       (0x00000400u)
#define CSL_GPIO_IN_DATA_IN10_SHIFT      (0x0000000Au)
#define CSL_GPIO_IN_DATA_IN10_RESETVAL   (0x00000000u)

#define CSL_GPIO_IN_DATA_IN9_MASK        (0x00000200u)
#define CSL_GPIO_IN_DATA_IN9_SHIFT       (0x00000009u)
#define CSL_GPIO_IN_DATA_IN9_RESETVAL    (0x00000000u)

#define CSL_GPIO_IN_DATA_IN8_MASK        (0x00000100u)
#define CSL_GPIO_IN_DATA_IN8_SHIFT       (0x00000008u)
#define CSL_GPIO_IN_DATA_IN8_RESETVAL    (0x00000000u)

#define CSL_GPIO_IN_DATA_IN7_MASK        (0x00000080u)
#define CSL_GPIO_IN_DATA_IN7_SHIFT       (0x00000007u)
#define CSL_GPIO_IN_DATA_IN7_RESETVAL    (0x00000000u)

#define CSL_GPIO_IN_DATA_IN6_MASK        (0x00000040u)
#define CSL_GPIO_IN_DATA_IN6_SHIFT       (0x00000006u)
#define CSL_GPIO_IN_DATA_IN6_RESETVAL    (0x00000000u)

#define CSL_GPIO_IN_DATA_IN5_MASK        (0x00000020u)
#define CSL_GPIO_IN_DATA_IN5_SHIFT       (0x00000005u)
#define CSL_GPIO_IN_DATA_IN5_RESETVAL    (0x00000000u)

#define CSL_GPIO_IN_DATA_IN4_MASK        (0x00000010u)
#define CSL_GPIO_IN_DATA_IN4_SHIFT       (0x00000004u)
#define CSL_GPIO_IN_DATA_IN4_RESETVAL    (0x00000000u)

#define CSL_GPIO_IN_DATA_IN3_MASK        (0x00000008u)
#define CSL_GPIO_IN_DATA_IN3_SHIFT       (0x00000003u)
#define CSL_GPIO_IN_DATA_IN3_RESETVAL    (0x00000000u)

#define CSL_GPIO_IN_DATA_IN2_MASK        (0x00000004u)
#define CSL_GPIO_IN_DATA_IN2_SHIFT       (0x00000002u)
#define CSL_GPIO_IN_DATA_IN2_RESETVAL    (0x00000000u)

#define CSL_GPIO_IN_DATA_IN1_MASK        (0x00000002u)
#define CSL_GPIO_IN_DATA_IN1_SHIFT       (0x00000001u)
#define CSL_GPIO_IN_DATA_IN1_RESETVAL    (0x00000000u)

#define CSL_GPIO_IN_DATA_IN0_MASK        (0x00000001u)
#define CSL_GPIO_IN_DATA_IN0_SHIFT       (0x00000000u)
#define CSL_GPIO_IN_DATA_IN0_RESETVAL    (0x00000000u)

#define CSL_GPIO_IN_DATA_RESETVAL        (0x00000000u)

/* SET_RIS_TRIG */

#define CSL_GPIO_SET_RIS_TRIG_SETRIS15_MASK (0x00008000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS15_SHIFT (0x0000000Fu)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS15_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS14_MASK (0x00004000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS14_SHIFT (0x0000000Eu)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS14_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS13_MASK (0x00002000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS13_SHIFT (0x0000000Du)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS13_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS12_MASK (0x00001000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS12_SHIFT (0x0000000Cu)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS12_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS11_MASK (0x00000800u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS11_SHIFT (0x0000000Bu)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS11_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS10_MASK (0x00000400u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS10_SHIFT (0x0000000Au)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS10_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS9_MASK (0x00000200u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS9_SHIFT (0x00000009u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS9_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS8_MASK (0x00000100u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS8_SHIFT (0x00000008u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS8_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS7_MASK (0x00000080u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS7_SHIFT (0x00000007u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS7_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS6_MASK (0x00000040u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS6_SHIFT (0x00000006u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS6_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS5_MASK (0x00000020u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS5_SHIFT (0x00000005u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS5_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS4_MASK (0x00000010u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS4_SHIFT (0x00000004u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS4_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS3_MASK (0x00000008u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS3_SHIFT (0x00000003u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS3_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS2_MASK (0x00000004u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS2_SHIFT (0x00000002u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS2_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS1_MASK (0x00000002u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS1_SHIFT (0x00000001u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS1_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS0_MASK (0x00000001u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS0_SHIFT (0x00000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS0_RESETVAL (0x00000000u)

/*----SETRIS Tokens----*/
#define CSL_GPIO_SET_RIS_TRIG_SETRIS_ENABLE (0x00000001u)

#define CSL_GPIO_SET_RIS_TRIG_RESETVAL   (0x00000000u)

/* CLR_RIS_TRIG */

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS15_MASK (0x00008000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS15_SHIFT (0x0000000Fu)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS15_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS14_MASK (0x00004000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS14_SHIFT (0x0000000Eu)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS14_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS13_MASK (0x00002000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS13_SHIFT (0x0000000Du)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS13_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS12_MASK (0x00001000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS12_SHIFT (0x0000000Cu)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS12_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS11_MASK (0x00000800u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS11_SHIFT (0x0000000Bu)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS11_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS10_MASK (0x00000400u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS10_SHIFT (0x0000000Au)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS10_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS9_MASK (0x00000200u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS9_SHIFT (0x00000009u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS9_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS8_MASK (0x00000100u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS8_SHIFT (0x00000008u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS8_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS7_MASK (0x00000080u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS7_SHIFT (0x00000007u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS7_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS6_MASK (0x00000040u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS6_SHIFT (0x00000006u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS6_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS5_MASK (0x00000020u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS5_SHIFT (0x00000005u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS5_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS4_MASK (0x00000010u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS4_SHIFT (0x00000004u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS4_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS3_MASK (0x00000008u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS3_SHIFT (0x00000003u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS3_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS2_MASK (0x00000004u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS2_SHIFT (0x00000002u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS2_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS1_MASK (0x00000002u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS1_SHIFT (0x00000001u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS1_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS0_MASK (0x00000001u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS0_SHIFT (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS0_RESETVAL (0x00000000u)

/*----CLRRIS Tokens----*/
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS_DISABLE (0x00000000u)

#define CSL_GPIO_CLR_RIS_TRIG_RESETVAL   (0x00000000u)

/* SET_FAL_TRIG */

#define CSL_GPIO_SET_FAL_TRIG_SETFAL15_MASK (0x00008000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL15_SHIFT (0x0000000Fu)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL15_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL14_MASK (0x00004000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL14_SHIFT (0x0000000Eu)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL14_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL13_MASK (0x00002000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL13_SHIFT (0x0000000Du)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL13_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL12_MASK (0x00001000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL12_SHIFT (0x0000000Cu)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL12_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL11_MASK (0x00000800u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL11_SHIFT (0x0000000Bu)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL11_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL10_MASK (0x00000400u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL10_SHIFT (0x0000000Au)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL10_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL9_MASK (0x00000200u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL9_SHIFT (0x00000009u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL9_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL8_MASK (0x00000100u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL8_SHIFT (0x00000008u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL8_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL7_MASK (0x00000080u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL7_SHIFT (0x00000007u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL7_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL6_MASK (0x00000040u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL6_SHIFT (0x00000006u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL6_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL5_MASK (0x00000020u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL5_SHIFT (0x00000005u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL5_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL4_MASK (0x00000010u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL4_SHIFT (0x00000004u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL4_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL3_MASK (0x00000008u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL3_SHIFT (0x00000003u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL3_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL2_MASK (0x00000004u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL2_SHIFT (0x00000002u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL2_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL1_MASK (0x00000002u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL1_SHIFT (0x00000001u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL1_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL0_MASK (0x00000001u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL0_SHIFT (0x00000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL0_RESETVAL (0x00000000u)

/*----SETFAL Tokens----*/
#define CSL_GPIO_SET_FAL_TRIG_SETFAL_ENABLE (0x00000001u)

#define CSL_GPIO_SET_FAL_TRIG_RESETVAL   (0x00000000u)

/* CLR_FAL_TRIG */

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL15_MASK (0x00008000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL15_SHIFT (0x0000000Fu)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL15_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL14_MASK (0x00004000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL14_SHIFT (0x0000000Eu)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL14_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL13_MASK (0x00002000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL13_SHIFT (0x0000000Du)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL13_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL12_MASK (0x00001000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL12_SHIFT (0x0000000Cu)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL12_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL11_MASK (0x00000800u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL11_SHIFT (0x0000000Bu)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL11_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL10_MASK (0x00000400u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL10_SHIFT (0x0000000Au)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL10_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL9_MASK (0x00000200u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL9_SHIFT (0x00000009u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL9_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL8_MASK (0x00000100u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL8_SHIFT (0x00000008u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL8_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL7_MASK (0x00000080u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL7_SHIFT (0x00000007u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL7_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL6_MASK (0x00000040u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL6_SHIFT (0x00000006u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL6_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL5_MASK (0x00000020u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL5_SHIFT (0x00000005u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL5_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL4_MASK (0x00000010u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL4_SHIFT (0x00000004u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL4_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL3_MASK (0x00000008u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL3_SHIFT (0x00000003u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL3_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL2_MASK (0x00000004u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL2_SHIFT (0x00000002u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL2_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL1_MASK (0x00000002u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL1_SHIFT (0x00000001u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL1_RESETVAL (0x00000000u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL0_MASK (0x00000001u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL0_SHIFT (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL0_RESETVAL (0x00000000u)

/*----CLRFAL Tokens----*/
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL_DISABLE (0x00000000u)

#define CSL_GPIO_CLR_FAL_TRIG_RESETVAL   (0x00000000u)

#endif