📄 cslr_gpio.h
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/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_gpio.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for GPIO
*/
#ifndef _CSLR_GPIO_H_
#define _CSLR_GPIO_H_
#include <cslr.h>
#include <tistdtypes.h>
#define CSL_GPIO_NUM_PINS (16)
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint8 RSVD0[8];
volatile Uint32 BINTEN;
volatile Uint8 RSVD1[4];
volatile Uint32 DIR;
volatile Uint32 OUT_DATA;
volatile Uint32 SET_DATA;
volatile Uint32 CLR_DATA;
volatile Uint32 IN_DATA;
volatile Uint32 SET_RIS_TRIG;
volatile Uint32 CLR_RIS_TRIG;
volatile Uint32 SET_FAL_TRIG;
volatile Uint32 CLR_FAL_TRIG;
} CSL_GpioRegs;
/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_GpioRegs *CSL_GpioRegsOvly;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* BINTEN */
#define CSL_GPIO_BINTEN_EN_MASK (0x00000001u)
#define CSL_GPIO_BINTEN_EN_SHIFT (0x00000000u)
#define CSL_GPIO_BINTEN_EN_RESETVAL (0x00000000u)
/*----EN Tokens----*/
#define CSL_GPIO_BINTEN_EN_DISABLE (0x00000000u)
#define CSL_GPIO_BINTEN_EN_ENABLE (0x00000001u)
#define CSL_GPIO_BINTEN_RESETVAL (0x00000000u)
/* DIR */
#define CSL_GPIO_DIR_DIR15_MASK (0x00008000u)
#define CSL_GPIO_DIR_DIR15_SHIFT (0x0000000Fu)
#define CSL_GPIO_DIR_DIR15_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR14_MASK (0x00004000u)
#define CSL_GPIO_DIR_DIR14_SHIFT (0x0000000Eu)
#define CSL_GPIO_DIR_DIR14_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR13_MASK (0x00002000u)
#define CSL_GPIO_DIR_DIR13_SHIFT (0x0000000Du)
#define CSL_GPIO_DIR_DIR13_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR12_MASK (0x00001000u)
#define CSL_GPIO_DIR_DIR12_SHIFT (0x0000000Cu)
#define CSL_GPIO_DIR_DIR12_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR11_MASK (0x00000800u)
#define CSL_GPIO_DIR_DIR11_SHIFT (0x0000000Bu)
#define CSL_GPIO_DIR_DIR11_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR10_MASK (0x00000400u)
#define CSL_GPIO_DIR_DIR10_SHIFT (0x0000000Au)
#define CSL_GPIO_DIR_DIR10_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR9_MASK (0x00000200u)
#define CSL_GPIO_DIR_DIR9_SHIFT (0x00000009u)
#define CSL_GPIO_DIR_DIR9_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR8_MASK (0x00000100u)
#define CSL_GPIO_DIR_DIR8_SHIFT (0x00000008u)
#define CSL_GPIO_DIR_DIR8_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR7_MASK (0x00000080u)
#define CSL_GPIO_DIR_DIR7_SHIFT (0x00000007u)
#define CSL_GPIO_DIR_DIR7_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR6_MASK (0x00000040u)
#define CSL_GPIO_DIR_DIR6_SHIFT (0x00000006u)
#define CSL_GPIO_DIR_DIR6_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR5_MASK (0x00000020u)
#define CSL_GPIO_DIR_DIR5_SHIFT (0x00000005u)
#define CSL_GPIO_DIR_DIR5_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR4_MASK (0x00000010u)
#define CSL_GPIO_DIR_DIR4_SHIFT (0x00000004u)
#define CSL_GPIO_DIR_DIR4_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR3_MASK (0x00000008u)
#define CSL_GPIO_DIR_DIR3_SHIFT (0x00000003u)
#define CSL_GPIO_DIR_DIR3_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR2_MASK (0x00000004u)
#define CSL_GPIO_DIR_DIR2_SHIFT (0x00000002u)
#define CSL_GPIO_DIR_DIR2_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR1_MASK (0x00000002u)
#define CSL_GPIO_DIR_DIR1_SHIFT (0x00000001u)
#define CSL_GPIO_DIR_DIR1_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR0_MASK (0x00000001u)
#define CSL_GPIO_DIR_DIR0_SHIFT (0x00000000u)
#define CSL_GPIO_DIR_DIR0_RESETVAL (0x00000001u)
/*----DIR Tokens----*/
#define CSL_GPIO_DIR_DIR_OUT (0x00000000u)
#define CSL_GPIO_DIR_DIR_IN (0x00000001u)
#define CSL_GPIO_DIR_RESETVAL (0x0000FFFFu)
/* OUT_DATA */
#define CSL_GPIO_OUT_DATA_OUT15_MASK (0x00008000u)
#define CSL_GPIO_OUT_DATA_OUT15_SHIFT (0x0000000Fu)
#define CSL_GPIO_OUT_DATA_OUT15_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT14_MASK (0x00004000u)
#define CSL_GPIO_OUT_DATA_OUT14_SHIFT (0x0000000Eu)
#define CSL_GPIO_OUT_DATA_OUT14_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT13_MASK (0x00002000u)
#define CSL_GPIO_OUT_DATA_OUT13_SHIFT (0x0000000Du)
#define CSL_GPIO_OUT_DATA_OUT13_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT12_MASK (0x00001000u)
#define CSL_GPIO_OUT_DATA_OUT12_SHIFT (0x0000000Cu)
#define CSL_GPIO_OUT_DATA_OUT12_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT11_MASK (0x00000800u)
#define CSL_GPIO_OUT_DATA_OUT11_SHIFT (0x0000000Bu)
#define CSL_GPIO_OUT_DATA_OUT11_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT10_MASK (0x00000400u)
#define CSL_GPIO_OUT_DATA_OUT10_SHIFT (0x0000000Au)
#define CSL_GPIO_OUT_DATA_OUT10_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT9_MASK (0x00000200u)
#define CSL_GPIO_OUT_DATA_OUT9_SHIFT (0x00000009u)
#define CSL_GPIO_OUT_DATA_OUT9_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT8_MASK (0x00000100u)
#define CSL_GPIO_OUT_DATA_OUT8_SHIFT (0x00000008u)
#define CSL_GPIO_OUT_DATA_OUT8_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT7_MASK (0x00000080u)
#define CSL_GPIO_OUT_DATA_OUT7_SHIFT (0x00000007u)
#define CSL_GPIO_OUT_DATA_OUT7_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT6_MASK (0x00000040u)
#define CSL_GPIO_OUT_DATA_OUT6_SHIFT (0x00000006u)
#define CSL_GPIO_OUT_DATA_OUT6_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT5_MASK (0x00000020u)
#define CSL_GPIO_OUT_DATA_OUT5_SHIFT (0x00000005u)
#define CSL_GPIO_OUT_DATA_OUT5_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT4_MASK (0x00000010u)
#define CSL_GPIO_OUT_DATA_OUT4_SHIFT (0x00000004u)
#define CSL_GPIO_OUT_DATA_OUT4_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT3_MASK (0x00000008u)
#define CSL_GPIO_OUT_DATA_OUT3_SHIFT (0x00000003u)
#define CSL_GPIO_OUT_DATA_OUT3_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT2_MASK (0x00000004u)
#define CSL_GPIO_OUT_DATA_OUT2_SHIFT (0x00000002u)
#define CSL_GPIO_OUT_DATA_OUT2_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT1_MASK (0x00000002u)
#define CSL_GPIO_OUT_DATA_OUT1_SHIFT (0x00000001u)
#define CSL_GPIO_OUT_DATA_OUT1_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT0_MASK (0x00000001u)
#define CSL_GPIO_OUT_DATA_OUT0_SHIFT (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT0_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_RESETVAL (0x00000000u)
/* SET_DATA */
#define CSL_GPIO_SET_DATA_SET15_MASK (0x00008000u)
#define CSL_GPIO_SET_DATA_SET15_SHIFT (0x0000000Fu)
#define CSL_GPIO_SET_DATA_SET15_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET14_MASK (0x00004000u)
#define CSL_GPIO_SET_DATA_SET14_SHIFT (0x0000000Eu)
#define CSL_GPIO_SET_DATA_SET14_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET13_MASK (0x00002000u)
#define CSL_GPIO_SET_DATA_SET13_SHIFT (0x0000000Du)
#define CSL_GPIO_SET_DATA_SET13_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET12_MASK (0x00001000u)
#define CSL_GPIO_SET_DATA_SET12_SHIFT (0x0000000Cu)
#define CSL_GPIO_SET_DATA_SET12_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET11_MASK (0x00000800u)
#define CSL_GPIO_SET_DATA_SET11_SHIFT (0x0000000Bu)
#define CSL_GPIO_SET_DATA_SET11_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET10_MASK (0x00000400u)
#define CSL_GPIO_SET_DATA_SET10_SHIFT (0x0000000Au)
#define CSL_GPIO_SET_DATA_SET10_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET9_MASK (0x00000200u)
#define CSL_GPIO_SET_DATA_SET9_SHIFT (0x00000009u)
#define CSL_GPIO_SET_DATA_SET9_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET8_MASK (0x00000100u)
#define CSL_GPIO_SET_DATA_SET8_SHIFT (0x00000008u)
#define CSL_GPIO_SET_DATA_SET8_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET7_MASK (0x00000080u)
#define CSL_GPIO_SET_DATA_SET7_SHIFT (0x00000007u)
#define CSL_GPIO_SET_DATA_SET7_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET6_MASK (0x00000040u)
#define CSL_GPIO_SET_DATA_SET6_SHIFT (0x00000006u)
#define CSL_GPIO_SET_DATA_SET6_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET5_MASK (0x00000020u)
#define CSL_GPIO_SET_DATA_SET5_SHIFT (0x00000005u)
#define CSL_GPIO_SET_DATA_SET5_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET4_MASK (0x00000010u)
#define CSL_GPIO_SET_DATA_SET4_SHIFT (0x00000004u)
#define CSL_GPIO_SET_DATA_SET4_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET3_MASK (0x00000008u)
#define CSL_GPIO_SET_DATA_SET3_SHIFT (0x00000003u)
#define CSL_GPIO_SET_DATA_SET3_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET2_MASK (0x00000004u)
#define CSL_GPIO_SET_DATA_SET2_SHIFT (0x00000002u)
#define CSL_GPIO_SET_DATA_SET2_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET1_MASK (0x00000002u)
#define CSL_GPIO_SET_DATA_SET1_SHIFT (0x00000001u)
#define CSL_GPIO_SET_DATA_SET1_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET0_MASK (0x00000001u)
#define CSL_GPIO_SET_DATA_SET0_SHIFT (0x00000000u)
#define CSL_GPIO_SET_DATA_SET0_RESETVAL (0x00000000u)
/*----SET Tokens----*/
#define CSL_GPIO_SET_DATA_SET_SET (0x00000001u)
#define CSL_GPIO_SET_DATA_RESETVAL (0x00000000u)
/* CLR_DATA */
#define CSL_GPIO_CLR_DATA_CLR15_MASK (0x00008000u)
#define CSL_GPIO_CLR_DATA_CLR15_SHIFT (0x0000000Fu)
#define CSL_GPIO_CLR_DATA_CLR15_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR14_MASK (0x00004000u)
#define CSL_GPIO_CLR_DATA_CLR14_SHIFT (0x0000000Eu)
#define CSL_GPIO_CLR_DATA_CLR14_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR13_MASK (0x00002000u)
#define CSL_GPIO_CLR_DATA_CLR13_SHIFT (0x0000000Du)
#define CSL_GPIO_CLR_DATA_CLR13_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR12_MASK (0x00001000u)
#define CSL_GPIO_CLR_DATA_CLR12_SHIFT (0x0000000Cu)
#define CSL_GPIO_CLR_DATA_CLR12_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR11_MASK (0x00000800u)
#define CSL_GPIO_CLR_DATA_CLR11_SHIFT (0x0000000Bu)
#define CSL_GPIO_CLR_DATA_CLR11_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR10_MASK (0x00000400u)
#define CSL_GPIO_CLR_DATA_CLR10_SHIFT (0x0000000Au)
#define CSL_GPIO_CLR_DATA_CLR10_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR9_MASK (0x00000200u)
#define CSL_GPIO_CLR_DATA_CLR9_SHIFT (0x00000009u)
#define CSL_GPIO_CLR_DATA_CLR9_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR8_MASK (0x00000100u)
#define CSL_GPIO_CLR_DATA_CLR8_SHIFT (0x00000008u)
#define CSL_GPIO_CLR_DATA_CLR8_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR7_MASK (0x00000080u)
#define CSL_GPIO_CLR_DATA_CLR7_SHIFT (0x00000007u)
#define CSL_GPIO_CLR_DATA_CLR7_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR6_MASK (0x00000040u)
#define CSL_GPIO_CLR_DATA_CLR6_SHIFT (0x00000006u)
#define CSL_GPIO_CLR_DATA_CLR6_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR5_MASK (0x00000020u)
#define CSL_GPIO_CLR_DATA_CLR5_SHIFT (0x00000005u)
#define CSL_GPIO_CLR_DATA_CLR5_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR4_MASK (0x00000010u)
#define CSL_GPIO_CLR_DATA_CLR4_SHIFT (0x00000004u)
#define CSL_GPIO_CLR_DATA_CLR4_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR3_MASK (0x00000008u)
#define CSL_GPIO_CLR_DATA_CLR3_SHIFT (0x00000003u)
#define CSL_GPIO_CLR_DATA_CLR3_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR2_MASK (0x00000004u)
#define CSL_GPIO_CLR_DATA_CLR2_SHIFT (0x00000002u)
#define CSL_GPIO_CLR_DATA_CLR2_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR1_MASK (0x00000002u)
#define CSL_GPIO_CLR_DATA_CLR1_SHIFT (0x00000001u)
#define CSL_GPIO_CLR_DATA_CLR1_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR0_MASK (0x00000001u)
#define CSL_GPIO_CLR_DATA_CLR0_SHIFT (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR0_RESETVAL (0x00000000u)
/*----CLR Tokens----*/
#define CSL_GPIO_CLR_DATA_CLR_CLR (0x00000001u)
#define CSL_GPIO_CLR_DATA_RESETVAL (0x00000000u)
/* IN_DATA */
#define CSL_GPIO_IN_DATA_IN15_MASK (0x00008000u)
#define CSL_GPIO_IN_DATA_IN15_SHIFT (0x0000000Fu)
#define CSL_GPIO_IN_DATA_IN15_RESETVAL (0x00000000u)
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