📄 cslr_edma3tc.h
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/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_edma3tc.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for EDMA3TC
*/
#ifndef _CSLR_EDMA3TC_H_
#define _CSLR_EDMA3TC_H_
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Register Overlay Structure for DFIREG
\**************************************************************************/
typedef struct {
volatile Uint32 DFOPT;
volatile Uint32 DFSRC;
volatile Uint32 DFCNT;
volatile Uint32 DFDST;
volatile Uint32 DFBIDX;
volatile Uint32 DFMPPRXY;
volatile Uint8 RSVD0[40];
} CSL_Edma3tcDfiregRegs;
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 PID;
volatile Uint32 TCCFG;
volatile Uint8 RSVD0[248];
volatile Uint32 TCSTAT;
volatile Uint8 RSVD1[28];
volatile Uint32 ERRSTAT;
volatile Uint32 ERREN;
volatile Uint32 ERRCLR;
volatile Uint32 ERRDET;
volatile Uint32 ERRCMD;
volatile Uint8 RSVD2[12];
volatile Uint32 RDRATE;
volatile Uint8 RSVD3[252];
volatile Uint32 SAOPT;
volatile Uint32 SASRC;
volatile Uint32 SACNT;
volatile Uint32 SADST;
volatile Uint32 SABIDX;
volatile Uint32 SAMPPRXY;
volatile Uint32 SACNTRLD;
volatile Uint32 SASRCBREF;
volatile Uint32 SADSTBREF;
volatile Uint8 RSVD4[28];
volatile Uint32 DFCNTRLD;
volatile Uint32 DFSRCBREF;
volatile Uint32 DFDSTBREF;
volatile Uint8 RSVD5[116];
CSL_Edma3tcDfiregRegs DFIREG[4];
} CSL_Edma3tcRegs;
/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_Edma3tcRegs *CSL_Edma3tcRegsOvly;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* PID */
#define CSL_EDMA3TC_PID_PID_MASK (0xFFFFFFFFu)
#define CSL_EDMA3TC_PID_PID_SHIFT (0x00000000u)
#define CSL_EDMA3TC_PID_PID_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_PID_RESETVAL (0x00000000u)
/* TCCFG */
#define CSL_EDMA3TC_TCCFG_DREGDEPTH_MASK (0x00000300u)
#define CSL_EDMA3TC_TCCFG_DREGDEPTH_SHIFT (0x00000008u)
#define CSL_EDMA3TC_TCCFG_DREGDEPTH_RESETVAL (0x00000000u)
/*----DREGDEPTH Tokens----*/
#define CSL_EDMA3TC_TCCFG_DREGDEPTH_2ENTRY (0x00000001u)
#define CSL_EDMA3TC_TCCFG_DREGDEPTH_4ENTRY (0x00000002u)
#define CSL_EDMA3TC_TCCFG_BUSWIDTH_MASK (0x00000030u)
#define CSL_EDMA3TC_TCCFG_BUSWIDTH_SHIFT (0x00000004u)
#define CSL_EDMA3TC_TCCFG_BUSWIDTH_RESETVAL (0x00000000u)
/*----BUSWIDTH Tokens----*/
#define CSL_EDMA3TC_TCCFG_BUSWIDTH_16BYTE (0x00000002u)
#define CSL_EDMA3TC_TCCFG_FIFOSIZE_MASK (0x00000007u)
#define CSL_EDMA3TC_TCCFG_FIFOSIZE_SHIFT (0x00000000u)
#define CSL_EDMA3TC_TCCFG_FIFOSIZE_RESETVAL (0x00000000u)
/*----FIFOSIZE Tokens----*/
#define CSL_EDMA3TC_TCCFG_FIFOSIZE_128BYTE (0x00000002u)
#define CSL_EDMA3TC_TCCFG_FIFOSIZE_256BYTE (0x00000003u)
#define CSL_EDMA3TC_TCCFG_RESETVAL (0x00000000u)
/* TCSTAT */
#define CSL_EDMA3TC_TCSTAT_DFSTRTPTR_MASK (0x00003000u)
#define CSL_EDMA3TC_TCSTAT_DFSTRTPTR_SHIFT (0x0000000Cu)
#define CSL_EDMA3TC_TCSTAT_DFSTRTPTR_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_TCSTAT_DSTACTV_MASK (0x00000070u)
#define CSL_EDMA3TC_TCSTAT_DSTACTV_SHIFT (0x00000004u)
#define CSL_EDMA3TC_TCSTAT_DSTACTV_RESETVAL (0x00000000u)
/*----DSTACTV Tokens----*/
#define CSL_EDMA3TC_TCSTAT_DSTACTV_EMPTY (0x00000000u)
#define CSL_EDMA3TC_TCSTAT_DSTACTV_1TR (0x00000001u)
#define CSL_EDMA3TC_TCSTAT_DSTACTV_2TR (0x00000002u)
#define CSL_EDMA3TC_TCSTAT_DSTACTV_3TR (0x00000003u)
#define CSL_EDMA3TC_TCSTAT_DSTACTV_4TR (0x00000004u)
#define CSL_EDMA3TC_TCSTAT_WSACTV_MASK (0x00000004u)
#define CSL_EDMA3TC_TCSTAT_WSACTV_SHIFT (0x00000002u)
#define CSL_EDMA3TC_TCSTAT_WSACTV_RESETVAL (0x00000000u)
/*----WSACTV Tokens----*/
#define CSL_EDMA3TC_TCSTAT_WSACTV_NONE (0x00000000u)
#define CSL_EDMA3TC_TCSTAT_WSACTV_PEND (0x00000001u)
#define CSL_EDMA3TC_TCSTAT_SRCACTV_MASK (0x00000002u)
#define CSL_EDMA3TC_TCSTAT_SRCACTV_SHIFT (0x00000001u)
#define CSL_EDMA3TC_TCSTAT_SRCACTV_RESETVAL (0x00000000u)
/*----SRCACTV Tokens----*/
#define CSL_EDMA3TC_TCSTAT_SRCACTV_IDLE (0x00000000u)
#define CSL_EDMA3TC_TCSTAT_SRCACTV_BUSY (0x00000001u)
#define CSL_EDMA3TC_TCSTAT_PROGBUSY_MASK (0x00000001u)
#define CSL_EDMA3TC_TCSTAT_PROGBUSY_SHIFT (0x00000000u)
#define CSL_EDMA3TC_TCSTAT_PROGBUSY_RESETVAL (0x00000000u)
/*----PROGBUSY Tokens----*/
#define CSL_EDMA3TC_TCSTAT_PROGBUSY_IDLE (0x00000000u)
#define CSL_EDMA3TC_TCSTAT_PROGBUSY_BUSY (0x00000001u)
#define CSL_EDMA3TC_TCSTAT_RESETVAL (0x00000100u)
/* ERRSTAT */
#define CSL_EDMA3TC_ERRSTAT_MMRAERR_MASK (0x00000008u)
#define CSL_EDMA3TC_ERRSTAT_MMRAERR_SHIFT (0x00000003u)
#define CSL_EDMA3TC_ERRSTAT_MMRAERR_RESETVAL (0x00000000u)
/*----MMRAERR Tokens----*/
#define CSL_EDMA3TC_ERRSTAT_MMRAERR_NONE (0x00000000u)
#define CSL_EDMA3TC_ERRSTAT_MMRAERR_ERROR (0x00000001u)
#define CSL_EDMA3TC_ERRSTAT_TRERR_MASK (0x00000004u)
#define CSL_EDMA3TC_ERRSTAT_TRERR_SHIFT (0x00000002u)
#define CSL_EDMA3TC_ERRSTAT_TRERR_RESETVAL (0x00000000u)
/*----TRERR Tokens----*/
#define CSL_EDMA3TC_ERRSTAT_TRERR_NONE (0x00000000u)
#define CSL_EDMA3TC_ERRSTAT_TRERR_ERROR (0x00000001u)
#define CSL_EDMA3TC_ERRSTAT_BUSERR_MASK (0x00000001u)
#define CSL_EDMA3TC_ERRSTAT_BUSERR_SHIFT (0x00000000u)
#define CSL_EDMA3TC_ERRSTAT_BUSERR_RESETVAL (0x00000000u)
/*----BUSERR Tokens----*/
#define CSL_EDMA3TC_ERRSTAT_BUSERR_NONE (0x00000000u)
#define CSL_EDMA3TC_ERRSTAT_BUSERR_ERROR (0x00000001u)
#define CSL_EDMA3TC_ERRSTAT_RESETVAL (0x00000000u)
/* ERREN */
#define CSL_EDMA3TC_ERREN_MMRAERR_MASK (0x00000008u)
#define CSL_EDMA3TC_ERREN_MMRAERR_SHIFT (0x00000003u)
#define CSL_EDMA3TC_ERREN_MMRAERR_RESETVAL (0x00000000u)
/*----MMRAERR Tokens----*/
#define CSL_EDMA3TC_ERREN_MMRAERR_ENABLE (0x00000001u)
#define CSL_EDMA3TC_ERREN_MMRAERR_DISABLE (0x00000000u)
#define CSL_EDMA3TC_ERREN_TRERR_MASK (0x00000004u)
#define CSL_EDMA3TC_ERREN_TRERR_SHIFT (0x00000002u)
#define CSL_EDMA3TC_ERREN_TRERR_RESETVAL (0x00000000u)
/*----TRERR Tokens----*/
#define CSL_EDMA3TC_ERREN_TRERR_ENABLE (0x00000001u)
#define CSL_EDMA3TC_ERREN_TRERR_DISABLE (0x00000000u)
#define CSL_EDMA3TC_ERREN_BUSERR_MASK (0x00000001u)
#define CSL_EDMA3TC_ERREN_BUSERR_SHIFT (0x00000000u)
#define CSL_EDMA3TC_ERREN_BUSERR_RESETVAL (0x00000000u)
/*----BUSERR Tokens----*/
#define CSL_EDMA3TC_ERREN_BUSERR_ENABLE (0x00000001u)
#define CSL_EDMA3TC_ERREN_BUSERR_DISABLE (0x00000000u)
#define CSL_EDMA3TC_ERREN_RESETVAL (0x00000000u)
/* ERRCLR */
#define CSL_EDMA3TC_ERRCLR_MMRAERR_MASK (0x00000008u)
#define CSL_EDMA3TC_ERRCLR_MMRAERR_SHIFT (0x00000003u)
#define CSL_EDMA3TC_ERRCLR_MMRAERR_RESETVAL (0x00000000u)
/*----MMRAERR Tokens----*/
#define CSL_EDMA3TC_ERRCLR_MMRAERR_CLEAR (0x00000001u)
#define CSL_EDMA3TC_ERRCLR_TRERR_MASK (0x00000004u)
#define CSL_EDMA3TC_ERRCLR_TRERR_SHIFT (0x00000002u)
#define CSL_EDMA3TC_ERRCLR_TRERR_RESETVAL (0x00000000u)
/*----TRERR Tokens----*/
#define CSL_EDMA3TC_ERRCLR_TRERR_CLEAR (0x00000001u)
#define CSL_EDMA3TC_ERRCLR_BUSERR_MASK (0x00000001u)
#define CSL_EDMA3TC_ERRCLR_BUSERR_SHIFT (0x00000000u)
#define CSL_EDMA3TC_ERRCLR_BUSERR_RESETVAL (0x00000000u)
/*----BUSERR Tokens----*/
#define CSL_EDMA3TC_ERRCLR_BUSERR_CLEAR (0x00000001u)
#define CSL_EDMA3TC_ERRCLR_RESETVAL (0x00000000u)
/* ERRDET */
#define CSL_EDMA3TC_ERRDET_TCCHEN_MASK (0x00020000u)
#define CSL_EDMA3TC_ERRDET_TCCHEN_SHIFT (0x00000011u)
#define CSL_EDMA3TC_ERRDET_TCCHEN_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_ERRDET_TCINTEN_MASK (0x00010000u)
#define CSL_EDMA3TC_ERRDET_TCINTEN_SHIFT (0x00000010u)
#define CSL_EDMA3TC_ERRDET_TCINTEN_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_ERRDET_TCC_MASK (0x00003F00u)
#define CSL_EDMA3TC_ERRDET_TCC_SHIFT (0x00000008u)
#define CSL_EDMA3TC_ERRDET_TCC_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_ERRDET_STAT_MASK (0x0000000Fu)
#define CSL_EDMA3TC_ERRDET_STAT_SHIFT (0x00000000u)
#define CSL_EDMA3TC_ERRDET_STAT_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_ERRDET_RESETVAL (0x00000000u)
/* ERRCMD */
#define CSL_EDMA3TC_ERRCMD_EVAL_MASK (0x00000001u)
#define CSL_EDMA3TC_ERRCMD_EVAL_SHIFT (0x00000000u)
#define CSL_EDMA3TC_ERRCMD_EVAL_RESETVAL (0x00000000u)
/*----EVAL Tokens----*/
#define CSL_EDMA3TC_ERRCMD_EVAL_EVAL (0x00000001u)
#define CSL_EDMA3TC_ERRCMD_RESETVAL (0x00000000u)
/* RDRATE */
#define CSL_EDMA3TC_RDRATE_RDRATE_MASK (0x00000007u)
#define CSL_EDMA3TC_RDRATE_RDRATE_SHIFT (0x00000000u)
#define CSL_EDMA3TC_RDRATE_RDRATE_RESETVAL (0x00000000u)
/*----RDRATE Tokens----*/
#define CSL_EDMA3TC_RDRATE_RDRATE_AFAP (0x00000000u)
#define CSL_EDMA3TC_RDRATE_RDRATE_4CYCLE (0x00000001u)
#define CSL_EDMA3TC_RDRATE_RDRATE_8CYCLE (0x00000002u)
#define CSL_EDMA3TC_RDRATE_RDRATE_16CYCLE (0x00000003u)
#define CSL_EDMA3TC_RDRATE_RDRATE_32CYCLE (0x00000004u)
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