cslr_edma3cc.h

Dm6455 driver,magbe useful to you!

#define CSL_EDMA3CC_EMCRH_E34_SHIFT      (0x00000002u)
#define CSL_EDMA3CC_EMCRH_E34_RESETVAL   (0x00000000u)

/*----E34 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E34_CLEAR      (0x00000001u)

#define CSL_EDMA3CC_EMCRH_E33_MASK       (0x00000002u)
#define CSL_EDMA3CC_EMCRH_E33_SHIFT      (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E33_RESETVAL   (0x00000000u)

/*----E33 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E33_CLEAR      (0x00000001u)

#define CSL_EDMA3CC_EMCRH_E32_MASK       (0x00000001u)
#define CSL_EDMA3CC_EMCRH_E32_SHIFT      (0x00000000u)
#define CSL_EDMA3CC_EMCRH_E32_RESETVAL   (0x00000000u)

/*----E32 Tokens----*/
#define CSL_EDMA3CC_EMCRH_E32_CLEAR      (0x00000001u)

#define CSL_EDMA3CC_EMCRH_RESETVAL       (0x00000000u)

/* QEMR */

#define CSL_EDMA3CC_QEMR_E3_MASK         (0x00000008u)
#define CSL_EDMA3CC_QEMR_E3_SHIFT        (0x00000003u)
#define CSL_EDMA3CC_QEMR_E3_RESETVAL     (0x00000000u)

#define CSL_EDMA3CC_QEMR_E2_MASK         (0x00000004u)
#define CSL_EDMA3CC_QEMR_E2_SHIFT        (0x00000002u)
#define CSL_EDMA3CC_QEMR_E2_RESETVAL     (0x00000000u)

#define CSL_EDMA3CC_QEMR_E1_MASK         (0x00000002u)
#define CSL_EDMA3CC_QEMR_E1_SHIFT        (0x00000001u)
#define CSL_EDMA3CC_QEMR_E1_RESETVAL     (0x00000000u)

#define CSL_EDMA3CC_QEMR_E0_MASK         (0x00000001u)
#define CSL_EDMA3CC_QEMR_E0_SHIFT        (0x00000000u)
#define CSL_EDMA3CC_QEMR_E0_RESETVAL     (0x00000000u)

#define CSL_EDMA3CC_QEMR_RESETVAL        (0x00000000u)

/* QEMCR */

#define CSL_EDMA3CC_QEMCR_E3_MASK        (0x00000008u)
#define CSL_EDMA3CC_QEMCR_E3_SHIFT       (0x00000003u)
#define CSL_EDMA3CC_QEMCR_E3_RESETVAL    (0x00000000u)

/*----E3 Tokens----*/
#define CSL_EDMA3CC_QEMCR_E3_CLEAR       (0x00000001u)

#define CSL_EDMA3CC_QEMCR_E2_MASK        (0x00000004u)
#define CSL_EDMA3CC_QEMCR_E2_SHIFT       (0x00000002u)
#define CSL_EDMA3CC_QEMCR_E2_RESETVAL    (0x00000000u)

/*----E2 Tokens----*/
#define CSL_EDMA3CC_QEMCR_E2_CLEAR       (0x00000001u)

#define CSL_EDMA3CC_QEMCR_E1_MASK        (0x00000002u)
#define CSL_EDMA3CC_QEMCR_E1_SHIFT       (0x00000001u)
#define CSL_EDMA3CC_QEMCR_E1_RESETVAL    (0x00000000u)

/*----E1 Tokens----*/
#define CSL_EDMA3CC_QEMCR_E1_CLEAR       (0x00000001u)

#define CSL_EDMA3CC_QEMCR_E0_MASK        (0x00000001u)
#define CSL_EDMA3CC_QEMCR_E0_SHIFT       (0x00000000u)
#define CSL_EDMA3CC_QEMCR_E0_RESETVAL    (0x00000000u)

/*----E0 Tokens----*/
#define CSL_EDMA3CC_QEMCR_E0_CLEAR       (0x00000001u)

#define CSL_EDMA3CC_QEMCR_RESETVAL       (0x00000000u)

/* CCERR */

#define CSL_EDMA3CC_CCERR_TCCERR_MASK    (0x00010000u)
#define CSL_EDMA3CC_CCERR_TCCERR_SHIFT   (0x00000010u)
#define CSL_EDMA3CC_CCERR_TCCERR_RESETVAL (0x00000000u)

#define CSL_EDMA3CC_CCERR_QTHRXCD3_MASK  (0x00000008u)
#define CSL_EDMA3CC_CCERR_QTHRXCD3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_CCERR_QTHRXCD3_RESETVAL (0x00000000u)

#define CSL_EDMA3CC_CCERR_QTHRXCD2_MASK  (0x00000004u)
#define CSL_EDMA3CC_CCERR_QTHRXCD2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_CCERR_QTHRXCD2_RESETVAL (0x00000000u)

#define CSL_EDMA3CC_CCERR_QTHRXCD1_MASK  (0x00000002u)
#define CSL_EDMA3CC_CCERR_QTHRXCD1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_CCERR_QTHRXCD1_RESETVAL (0x00000000u)

#define CSL_EDMA3CC_CCERR_QTHRXCD0_MASK  (0x00000001u)
#define CSL_EDMA3CC_CCERR_QTHRXCD0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_CCERR_QTHRXCD0_RESETVAL (0x00000000u)

#define CSL_EDMA3CC_CCERR_RESETVAL       (0x00000000u)

/* CCERRCLR */

#define CSL_EDMA3CC_CCERRCLR_TCCERR_MASK (0x00010000u)
#define CSL_EDMA3CC_CCERRCLR_TCCERR_SHIFT (0x00000010u)
#define CSL_EDMA3CC_CCERRCLR_TCCERR_RESETVAL (0x00000000u)

/*----TCCERR Tokens----*/
#define CSL_EDMA3CC_CCERRCLR_TCCERR_CLEAR (0x00000001u)

#define CSL_EDMA3CC_CCERRCLR_QTHRXCD3_MASK (0x00000008u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD3_SHIFT (0x00000003u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD3_RESETVAL (0x00000000u)

/*----QTHRXCD3 Tokens----*/
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD3_CLEAR (0x00000001u)

#define CSL_EDMA3CC_CCERRCLR_QTHRXCD2_MASK (0x00000004u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD2_SHIFT (0x00000002u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD2_RESETVAL (0x00000000u)

/*----QTHRXCD2 Tokens----*/
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD2_CLEAR (0x00000001u)

#define CSL_EDMA3CC_CCERRCLR_QTHRXCD1_MASK (0x00000002u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD1_RESETVAL (0x00000000u)

/*----QTHRXCD1 Tokens----*/
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD1_CLEAR (0x00000001u)

#define CSL_EDMA3CC_CCERRCLR_QTHRXCD0_MASK (0x00000001u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD0_RESETVAL (0x00000000u)

/*----QTHRXCD0 Tokens----*/
#define CSL_EDMA3CC_CCERRCLR_QTHRXCD0_CLEAR (0x00000001u)

#define CSL_EDMA3CC_CCERRCLR_RESETVAL    (0x00000000u)

/* EEVAL */

#define CSL_EDMA3CC_EEVAL_EVAL_MASK      (0x00000001u)
#define CSL_EDMA3CC_EEVAL_EVAL_SHIFT     (0x00000000u)
#define CSL_EDMA3CC_EEVAL_EVAL_RESETVAL  (0x00000000u)

/*----EVAL Tokens----*/
#define CSL_EDMA3CC_EEVAL_EVAL_EVAL      (0x00000001u)

#define CSL_EDMA3CC_EEVAL_RESETVAL       (0x00000000u)

/* DRAE */

#define CSL_EDMA3CC_DRAE_E31_MASK        (0x80000000u)
#define CSL_EDMA3CC_DRAE_E31_SHIFT       (0x0000001Fu)
#define CSL_EDMA3CC_DRAE_E31_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E30_MASK        (0x40000000u)
#define CSL_EDMA3CC_DRAE_E30_SHIFT       (0x0000001Eu)
#define CSL_EDMA3CC_DRAE_E30_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E29_MASK        (0x20000000u)
#define CSL_EDMA3CC_DRAE_E29_SHIFT       (0x0000001Du)
#define CSL_EDMA3CC_DRAE_E29_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E28_MASK        (0x10000000u)
#define CSL_EDMA3CC_DRAE_E28_SHIFT       (0x0000001Cu)
#define CSL_EDMA3CC_DRAE_E28_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E27_MASK        (0x08000000u)
#define CSL_EDMA3CC_DRAE_E27_SHIFT       (0x0000001Bu)
#define CSL_EDMA3CC_DRAE_E27_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E26_MASK        (0x04000000u)
#define CSL_EDMA3CC_DRAE_E26_SHIFT       (0x0000001Au)
#define CSL_EDMA3CC_DRAE_E26_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E25_MASK        (0x02000000u)
#define CSL_EDMA3CC_DRAE_E25_SHIFT       (0x00000019u)
#define CSL_EDMA3CC_DRAE_E25_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E24_MASK        (0x01000000u)
#define CSL_EDMA3CC_DRAE_E24_SHIFT       (0x00000018u)
#define CSL_EDMA3CC_DRAE_E24_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E23_MASK        (0x00800000u)
#define CSL_EDMA3CC_DRAE_E23_SHIFT       (0x00000017u)
#define CSL_EDMA3CC_DRAE_E23_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E22_MASK        (0x00400000u)
#define CSL_EDMA3CC_DRAE_E22_SHIFT       (0x00000016u)
#define CSL_EDMA3CC_DRAE_E22_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E21_MASK        (0x00200000u)
#define CSL_EDMA3CC_DRAE_E21_SHIFT       (0x00000015u)
#define CSL_EDMA3CC_DRAE_E21_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E20_MASK        (0x00100000u)
#define CSL_EDMA3CC_DRAE_E20_SHIFT       (0x00000014u)
#define CSL_EDMA3CC_DRAE_E20_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E19_MASK        (0x00080000u)
#define CSL_EDMA3CC_DRAE_E19_SHIFT       (0x00000013u)
#define CSL_EDMA3CC_DRAE_E19_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E18_MASK        (0x00040000u)
#define CSL_EDMA3CC_DRAE_E18_SHIFT       (0x00000012u)
#define CSL_EDMA3CC_DRAE_E18_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E17_MASK        (0x00020000u)
#define CSL_EDMA3CC_DRAE_E17_SHIFT       (0x00000011u)
#define CSL_EDMA3CC_DRAE_E17_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E16_MASK        (0x00010000u)
#define CSL_EDMA3CC_DRAE_E16_SHIFT       (0x00000010u)
#define CSL_EDMA3CC_DRAE_E16_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E15_MASK        (0x00008000u)
#define CSL_EDMA3CC_DRAE_E15_SHIFT       (0x0000000Fu)
#define CSL_EDMA3CC_DRAE_E15_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E14_MASK        (0x00004000u)
#define CSL_EDMA3CC_DRAE_E14_SHIFT       (0x0000000Eu)
#define CSL_EDMA3CC_DRAE_E14_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E13_MASK        (0x00002000u)
#define CSL_EDMA3CC_DRAE_E13_SHIFT       (0x0000000Du)
#define CSL_EDMA3CC_DRAE_E13_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E12_MASK        (0x00001000u)
#define CSL_EDMA3CC_DRAE_E12_SHIFT       (0x0000000Cu)
#define CSL_EDMA3CC_DRAE_E12_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E11_MASK        (0x00000800u)
#define CSL_EDMA3CC_DRAE_E11_SHIFT       (0x0000000Bu)
#define CSL_EDMA3CC_DRAE_E11_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E10_MASK        (0x00000400u)
#define CSL_EDMA3CC_DRAE_E10_SHIFT       (0x0000000Au)
#define CSL_EDMA3CC_DRAE_E10_RESETVAL    (0x00000000u)

#define CSL_EDMA3CC_DRAE_E9_MASK         (0x00000200u)
#define CSL_EDMA3CC_DRAE_E9_SHIFT        (0x00000009u)
#define CSL_EDMA3CC_DRAE_E9_RESETVAL     (0x00000000u)

#define CSL_EDMA3CC_DRAE_E8_MASK         (0x00000100u)
#define CSL_EDMA3CC_DRAE_E8_SHIFT        (0x00000008u)
#define CSL_EDMA3CC_DRAE_E8_RESETVAL     (0x00000000u)

#define CSL_EDMA3CC_DRAE_E7_MASK         (0x00000080u)
#define CSL_EDMA3CC_DRAE_E7_SHIFT        (0x00000007u)
#define CSL_EDMA3CC_DRAE_E7_RESETVAL     (0x00000000u)

#define CSL_EDMA3CC_DRAE_E6_MASK         (0x00000040u)
#define CSL_EDMA3CC_DRAE_E6_SHIFT        (0x00000006u)
#define CSL_EDMA3CC_DRAE_E6_RESETVAL     (0x00000000u)

#define CSL_EDMA3CC_DRAE_E5_MASK         (0x00000020u)
#define CSL_EDMA3CC_DRAE_E5_SHIFT        (0x00000005u)
#define CSL_EDMA3CC_DRAE_E5_RESETVAL     (0x00000000u)

#define CSL_EDMA3CC_DRAE_E4_MASK         (0x00000010u)
#define CSL_EDMA3CC_DRAE_E4_SHIFT        (0x00000004u)
#define CSL_EDMA3CC_DRAE_E4_RESETVAL     (0x00000000u)

#define CSL_EDMA3CC_DRAE_E3_MASK         (0x00000008u)
#define CSL_EDMA3CC_DRAE_E3_SHIFT        (0x00000003u)
#define CSL_EDMA3CC_DRAE_E3_RESETVAL     (0x00000000u)

#define CSL_EDMA3CC_DRAE_E2_MASK         (0x00000004u)
#define CSL_EDMA3CC_DRAE_E2_SHIFT        (0x00000002u)
#define CSL_EDMA3CC_DRAE_E2_RESETVAL     (0x00000000u)

#define CSL_EDMA3CC_DRAE_E1_MASK         (0x00000002u)
#define CSL_EDMA3CC_DRAE_E1_SHIFT        (0x00000001u)
#define CSL_EDMA3CC_DRAE_E1_RESETVAL     (0x00000000u)

#define CSL_EDMA3CC_DRAE_E0_MASK         (0x00000001u)
#define CSL_EDMA3CC_DRAE_E0_SHIFT        (0x00000000u)
#define CSL_EDMA3CC_DRAE_E0_RESETVAL     (0x00000000u)

#define CSL_EDMA3CC_DRAE_RESETVAL        (0x00000000u)

/* DRAEH */

#define CSL_EDMA3CC_DRAEH_E63_MASK       (0x80000000u)
#define CSL_EDMA3CC_DRAEH_E63_SHIFT      (0x0000001Fu)
#define CSL_EDMA3CC_DRAEH_E63_RESETVAL   (0x00000000u)

#define CSL_EDMA3CC_DRAEH_E62_MASK       (0x40000000u)
#define CSL_EDMA3CC_DRAEH_E62_SHIFT      (0x0000001Eu)
#define CSL_EDMA3CC_DRAEH_E62_RESETVAL   (0x00000000u)

#define CSL_EDMA3CC_DRAEH_E61_MASK       (0x20000000u)
#define CSL_EDMA3CC_DRAEH_E61_SHIFT      (0x0000001Du)
#define CSL_EDMA3CC_DRAEH_E61_RESETVAL   (0x00000000u)

#define CSL_EDMA3CC_DRAEH_E60_MASK       (0x10000000u)
#define CSL_EDMA3CC_DRAEH_E60_SHIFT      (0x0000001Cu)
#define CSL_EDMA3CC_DRAEH_E60_RESETVAL   (0x00000000u)

#define CSL_EDMA3CC_DRAEH_E59_MASK       (0x08000000u)
#define CSL_EDMA3CC_DRAEH_E59_SHIFT      (0x0000001Bu)
#define CSL_EDMA3CC_DRAEH_E59_RESETVAL   (0x00000000u)

#define CSL_EDMA3CC_DRAEH_E58_MASK       (0x04000000u)
#define CSL_EDMA3CC_DRAEH_E58_SHIFT      (0x0000001Au)
#define CSL_EDMA3CC_DRAEH_E58_RESETVAL   (0x00000000u)

#define CSL_EDMA3CC_DRAEH_E57_MASK       (0x02000000u)
#define CSL_EDMA3CC_DRAEH_E57_SHIFT      (0x00000019u)
#define CSL_EDMA3CC_DRAEH_E57_RESETVAL   (0x00000000u)

#define CSL_EDMA3CC_DRAEH_E56_MASK       (0x01000000u)
#define CSL_EDMA3CC_DRAEH_E56_SHIFT      (0x00000018u)
#define CSL_EDMA3CC_DRAEH_E56_RESETVAL   (0x00000000u)

#define CSL_EDMA3CC_DRAEH_E55_MASK       (0x00800000u)
#define CSL_EDMA3CC_DRAEH_E55_SHIFT      (0x00000017u)
#define CSL_EDMA3CC_DRAEH_E55_RESETVAL   (0x00000000u)

#define CSL_EDMA3CC_DRAEH_E54_MASK       (0x00400000u)
#define CSL_EDMA3CC_DRAEH_E54_SHIFT      (0x00000016u)
#define CSL_EDMA3CC_DRAEH_E54_RESETVAL   (0x00000000u)

#define CSL_EDMA3CC_DRAEH_E53_MASK       (0x00200000u)
#define CSL_EDMA3CC_DRAEH_E53_SHIFT      (0x00000015u)
#define CSL_EDMA3CC_DRAEH_E53_RESETVAL   (0x00000000u)

#define CSL_EDMA3CC_DRAEH_E52_MASK       (0x00100000u)
#define CSL_EDMA3CC_DRAEH_E52_SHIFT      (0x00000014u)
#define CSL_EDMA3CC_DRAEH_E52_RESETVAL   (0x00000000u)

#define CSL_EDMA3CC_DRAEH_E51_MASK       (0x00080000u)
#define CSL_EDMA3CC_DRAEH_E51_SHIFT      (0x00000013u)
#define CSL_EDMA3CC_DRAEH_E51_RESETVAL   (0x00000000u)

#define CSL_EDMA3CC_DRAEH_E50_MASK       (0x00040000u)
#define CSL_EDMA3CC_DRAEH_E50_SHIFT      (0x00000012u)
#define CSL_EDMA3CC_DRAEH_E50_RESETVAL   (0x00000000u)

#define CSL_EDMA3CC_DRAEH_E49_MASK       (0x00020000u)
#define CSL_EDMA3CC_DRAEH_E49_SHIFT      (0x00000011u)
#define CSL_EDMA3CC_DRAEH_E49_RESETVAL   (0x00000000u)

#define CSL_EDMA3CC_DRAEH_E48_MASK       (0x00010000u)
#define CSL_EDMA3CC_DRAEH_E48_SHIFT      (0x00000010u)
#define CSL_EDMA3CC_DRAEH_E48_RESETVAL   (0x00000000u)

#define CSL_EDMA3CC_DRAEH_E47_MASK       (0x00008000u)
#define CSL_EDMA3CC_DRAEH_E47_SHIFT      (0x0000000Fu)
#define CSL_EDMA3CC_DRAEH_E47_RESETVAL   (0x00000000u)