csl_ddr2.h

Dm6455 driver,magbe useful to you!

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
 *
 *   Use of this software is controlled by the terms and conditions found
 *   in the license agreement under which this software has been supplied.
 *  ============================================================================
 */
/** ============================================================================
 *  @file    csl_ddr2.h
 *
 *  @Path    $(CSLPATH)\inc
 *
 *  @desc    Header file for functional layer of CSL 
 *    - The different enumerations, structure definitions
 *      and function declarations
 * 
 */
/* =============================================================================
 *  Revision History
 *  ===============
 *  11-Apr-2005 RM  File Created.
 *  
 *  05-Oct-2005 NG  Updation done according to new register layer
 *  
 *  03-Feb-2006 ds  ddrDrive field added to CSL_Ddr2Settings 
 * =============================================================================
 */

/** 
 * @mainpage DDR2 EMIF CSL 3.x
 *
 * @section Introduction
 *
 * @subsection xxx Purpose and Scope
 * The purpose of this document is to identify a set of common CSL APIs for
 * the DDR2 EMIF module across various devices. The CSL developer is expected 
 * to refer to this document while designing APIs for these modules. Some of 
 * the cases listed APIs may not be applicable to a given DDR2 EMIF module. 
 * While other in this list of APIs may not be sufficient to cover all the 
 * features of a particular DDR2 EMIF Module. The CSL developer should use his 
 * discretion designing new APIs or extending the existing ones to cover these.
 *
 * @subsection aaa Terms and Abbreviations
 *   -# CSL:  Chip Support Library
 *   -# API:  Application Programmer Interface
 *
 * @subsection References
 *    -# EMIF_SPEC, EMIF Module Specifications Document; Version 3.16.1  
 *                  Jan 18,2005
 *
 */
#ifndef _CSL_DDR2_H_
#define _CSL_DDR2_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <cslr.h>
#include <soc.h>
#include <csl_error.h>
#include <csl_types.h>
#include <cslr_ddr2.h>

/*
 * The defaults of DDR2 SDRAM Timing1 Control structure
 */
#define CSL_DDR2_TIMING1_TRFC_DEFAULT    0x7F
#define CSL_DDR2_TIMING1_TRP_DEFAULT     0x07
#define CSL_DDR2_TIMING1_TRCD_DEFAULT    0x07
#define CSL_DDR2_TIMING1_TWR_DEFAULT     0x07
#define CSL_DDR2_TIMING1_TRAS_DEFAULT    0x1F
#define CSL_DDR2_TIMING1_TRC_DEFAULT     0x1F
#define CSL_DDR2_TIMING1_TRRD_DEFAULT    0x07
#define CSL_DDR2_TIMING1_TWTR_DEFAULT    0x03

/*
 * The defaults of DDR2 SDRAM Timing2 Control structure.
 */

#define CSL_DDR2_TIMING2_T_ODT_DEFAULT    0x03
#define CSL_DDR2_TIMING2_TSXNR_DEFAULT    0x7F
#define CSL_DDR2_TIMING2_TSXRD_DEFAULT    0xFF
#define CSL_DDR2_TIMING2_TRTP_DEFAULT     0x07
#define CSL_DDR2_TIMING2_TCKE_DEFAULT     0x1F

/*
 * The default values of SDRAM config, refresh, timing1 and timing2 registers 
 * which are other than the reset values.
 */
#define CSL_DDR2_SDCFG_DEFAULT     (0x00130630u)
#define CSL_DDR2_SDRFC_DEFAULT     (0x00000753u)
#define CSL_DDR2_SDTIM1_DEFAULT    (0x10912A09u)
#define CSL_DDR2_SDTIM2_DEFAULT    (0x00850566u)

/******************************************************************************
 * DDR2 global typedef declarations
 ******************************************************************************
 */

/** @brief Enumeration for bit field narrow_mode of SDRAM Config Register */ 
typedef enum {
    /** DDR2 SDRAM data bus width is 32 bits  */
    CSL_DDR2_NORMAL_MODE      = 0,
    
    /** DDR2 SDRAM data bus width is 16 bits   */
    CSL_DDR2_NARROW_MODE     = 1
}CSL_Ddr2Mode; 

/** @brief Enumeration for bit field cl of SDRAM Config Register */ 
typedef enum {
    /** Cas Latency is 2  */
    CSL_DDR2_CAS_LATENCY_2    = 2,
    
    /** Cas Latency is 3   */
    CSL_DDR2_CAS_LATENCY_3    = 3,
    
    /** Cas Latency is 4  */
    CSL_DDR2_CAS_LATENCY_4    = 4,
    
    /** Cas Latency is 5   */
    CSL_DDR2_CAS_LATENCY_5    = 5
} CSL_Ddr2CasLatency; 

/** @brief Enumeration for bit field ibank of SDRAM Config Register */ 
typedef enum {
    /** DDR2 SDRAM has one internal bank  */
    CSL_DDR2_1_SDRAM_BANKS    = 0,
    
    /** DDR2 SDRAM has two internal banks   */
    CSL_DDR2_2_SDRAM_BANKS    = 1,
    
    /** DDR2 SDRAM has four internal bank  */
    CSL_DDR2_4_SDRAM_BANKS    = 2,
    
    /** DDR2 SDRAM has eight internal banks   */
    CSL_DDR2_8_SDRAM_BANKS    = 3
} CSL_Ddr2IntBank; 

/** @brief Enumeration for bit field pagesize of SDRAM Config Register */ 
typedef enum {
    /** 256-word pages requiring 8 column address bits  */
    CSL_DDR2_256WORD_8COL_ADDR      = 0,
    
    /** 512-word pages requiring 9 column address bits  */
    CSL_DDR2_512WORD_9COL_ADDR      = 1,
    
    /** 1024-word pages requiring 10 column address bits */
    CSL_DDR2_1024WORD_10COL_ADDR    = 2,
    
    /** 2048-word pages requiring 11 column address bits */
    CSL_DDR2_2048WORD_11COL_ADDR    = 3
} CSL_Ddr2PageSize; 

/** @brief Enumeration for bit field SR of SDRAM Config Register */ 
typedef enum {
    /** Disables Self Refresh on DDR2  */
    CSL_DDR2_SELF_REFRESH_DISABLE    = 0,
    
    /** Connected DDR2 SDRAM device will enter Self Refresh Mode 
     *  and DDR2 EMIF enters Self Refresh State   
     */
    CSL_DDR2_SELF_REFRESH_ENABLE     = 1
} CSL_Ddr2SelfRefresh; 

/** @brief Enumeration for bit field ddr_drive of SDRAM Config Register */ 
typedef enum {
    /** Normal drive strength */
    CSL_DDR2_NORM_DRIVE      = 0,
    
    /** Weak drive strengths   */
    CSL_DDR2_WEAK_DRIVE     = 1
}CSL_Ddr2Drive; 

/** 
 *  @brief Module specific context information.  
 */
typedef struct {
    /** Context information of DDR2 external memory interface CSL passed as an
     *  argument to CSL_ddr2Init().Present implementation of DDR2 CSL doesn't 
     *  have any context information; hence assigned NULL.
     *  The below declaration is just a place-holder for future implementation.
     */
    Uint16    contextInfo;
    
} CSL_Ddr2Context;

/** 
 * @brief This structure contains the base-address information for the DDR2
 *        instance
 */
typedef struct {
    /** Base-address of the configuration registers of the peripheral */
    CSL_Ddr2RegsOvly    regs;
} CSL_Ddr2BaseAddress;


/** 
 * @brief This Object contains the reference to the instance of DDR2 opened
 *  using the @a CSL_ddr2Open().
 *
 *  The pointer to this, is passed to all DDR2 CSL APIs.
 */
typedef struct CSL_Ddr2Obj {
    /** This is a pointer to the registers of the instance of DDR2
     *  referred to by this object
     */
    CSL_Ddr2RegsOvly    regs;
    
    /** This is the instance of DDR2 being referred to by this object  */
    CSL_InstNum         perNum;    
} CSL_Ddr2Obj;

/** 
 * @brief this is a pointer to @a CSL_Ddr2Obj and is passed as the first
 *  parameter to all DDR2 CSL APIs
 */
typedef struct CSL_Ddr2Obj *CSL_Ddr2Handle;

/** 
 * @brief This is module specific parameters.  Present implementation of DDR2 
 *        CSL doesn't have any module specific parameters.
 */
typedef struct {
    /** Bit mask to be used for module specific parameters. The below
     *  declaration is just a place-holder for future implementation. Passed as 
     *  an argument to CSL_ddr2Open().
     */
    CSL_BitMask16    flags;
} CSL_Ddr2Param;

/** 
 * @brief DDR2 SDRAM Timing1 structure.
 * All fields needed for DDR2 SDRAM Timing1 are present in this structure.
 */
typedef struct {
    /** Specifies TRFC value: Minimum number of DDR2 EMIF cycles from Refresh 
     *  or Load command to Refresh or Activate command, minus one 
     */
    Uint8    trfc;
    /** Specifies TRP value: Minimum number of DDR2 EMIF cycles from Pre-charge
     *  to Active or Refresh command, minus one  
     */
    Uint8    trp;
    /** Specifies TRCD value: Minimum number of DDR2 EMIF cycles from Active to 
     *  Read or Write command, minus one  
     */
    Uint8    trcd;
    /** Specifies TWR value: Minimum number of DDR2 EMIF cycles from last write 
     *  transfer to Pre-charge command, minus one 
     */
    Uint8    twr;
    /** Specifies TRAS value: Minimum number of DDR2 EMIF cycles from Activate 
     *  to Pre-charge command, minus one  
     */
    Uint8    tras;
    /** Specifies TRC value: Minimum number of DDR2 EMIF cycles from Activate 
     *  command to Activate command, minus one 
     */
    Uint8    trc;
    /** Specifies TRRD value: Minimum number of DDR2 EMIF cycles from Activate 
     *  command to Activate command for a differnt bank, minus one 
     */
    Uint8    trrd;
    /** Specifies the minimum number of DDR2 EMIF clock cycles from last DDR 
     *  Write to DDR Read,  minus one        
     */
    Uint8    twtr;
} CSL_Ddr2Timing1;

/** @brief DDR2 SDRAM Timing2 structure.
 *
 * All fields needed for DDR2 SDRAM Timing2 are present in this structure.
 */
typedef struct {    
    /** Specifies the minimum number of DDR2 EMIF clock cycles from ODT enable 
     *  to write data driven for DDR2 SDRAM.          
     */
    Uint8    todt;
    /** Specifies the minimum number of DDR2 EMIF clock cycles from Self-Refresh
     *  exit to any command other than a Read command, minus one.
     */
    Uint8    tsxnr;
    /** Specifies the minimum number of DDR2 EMIF clock cycles from Self-Refresh
     *  exit to a Read command for DDR SDRAM, minus one.
     */
    Uint8    tsxrd;
    /** Specifies the minimum number of DDR2 EMIF clock cycles from the last 
     *  Read command to a Pre-charge command for DDR2 SDRAM, minus one.
     */
    Uint8    trtp;
    /** Specifies the minimum number of DDR2 EMIF clock cycles between 
     *  pado_mcke_o changes, minus one.
     */
    Uint8    tcke;
} CSL_Ddr2Timing2;

/** @brief DDR2 SDRAM Settings structure.
 *
 * All fields needed for DDR2 SDRAM settings are present in this structure.
 */
typedef struct {
    /** CAS Latency */
    CSL_Ddr2CasLatency    casLatncy;
    /** Defines number of banks inside connected SDRAM devices */
    CSL_Ddr2IntBank       ibank;
    /** Defines the internal page size of connected SDRAM devices */
    CSL_Ddr2PageSize      pageSize;     
    /** SDRAM data bus width */
    CSL_Ddr2Mode          narrowMode;
    /** DDR SDRAM drive strength */
    CSL_Ddr2Drive         ddrDrive;
} CSL_Ddr2Settings;

/** 
 * @brief This has all the fields required to configure DDR2 at Power Up
 *  (after a Hardware Reset) or a Soft Reset.  
 *
 *  This structure is used to setup or obtain existing setup of
 *  DDR2 using @a CSL_ddr2HwSetup() & @a CSL_ddr2GetHwSetup() functions
 *  respectively.