cslr_srio.h

Dm6455 driver,magbe useful to you!

#define CSL_SRIO_RX_CPPI_ICCR_ICC2_MASK  (0x00000004u)
#define CSL_SRIO_RX_CPPI_ICCR_ICC2_SHIFT (0x00000002u)
#define CSL_SRIO_RX_CPPI_ICCR_ICC2_RESETVAL (0x00000000u)

#define CSL_SRIO_RX_CPPI_ICCR_ICC1_MASK  (0x00000002u)
#define CSL_SRIO_RX_CPPI_ICCR_ICC1_SHIFT (0x00000001u)
#define CSL_SRIO_RX_CPPI_ICCR_ICC1_RESETVAL (0x00000000u)

#define CSL_SRIO_RX_CPPI_ICCR_ICC0_MASK  (0x00000001u)
#define CSL_SRIO_RX_CPPI_ICCR_ICC0_SHIFT (0x00000000u)
#define CSL_SRIO_RX_CPPI_ICCR_ICC0_RESETVAL (0x00000000u)

#define CSL_SRIO_RX_CPPI_ICCR_RESETVAL   (0x00000000u)

/* TX_CPPI_ICSR */

#define CSL_SRIO_TX_CPPI_ICSR_ICS15_MASK (0x00008000u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS15_SHIFT (0x0000000Fu)
#define CSL_SRIO_TX_CPPI_ICSR_ICS15_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICSR_ICS14_MASK (0x00004000u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS14_SHIFT (0x0000000Eu)
#define CSL_SRIO_TX_CPPI_ICSR_ICS14_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICSR_ICS13_MASK (0x00002000u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS13_SHIFT (0x0000000Du)
#define CSL_SRIO_TX_CPPI_ICSR_ICS13_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICSR_ICS12_MASK (0x00001000u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS12_SHIFT (0x0000000Cu)
#define CSL_SRIO_TX_CPPI_ICSR_ICS12_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICSR_ICS11_MASK (0x00000800u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS11_SHIFT (0x0000000Bu)
#define CSL_SRIO_TX_CPPI_ICSR_ICS11_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICSR_ICS10_MASK (0x00000400u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS10_SHIFT (0x0000000Au)
#define CSL_SRIO_TX_CPPI_ICSR_ICS10_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICSR_ICS9_MASK  (0x00000200u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS9_SHIFT (0x00000009u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS9_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICSR_ICS8_MASK  (0x00000100u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS8_SHIFT (0x00000008u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS8_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICSR_ICS7_MASK  (0x00000080u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS7_SHIFT (0x00000007u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS7_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICSR_ICS6_MASK  (0x00000040u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS6_SHIFT (0x00000006u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS6_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICSR_ICS5_MASK  (0x00000020u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS5_SHIFT (0x00000005u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS5_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICSR_ICS4_MASK  (0x00000010u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS4_SHIFT (0x00000004u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS4_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICSR_ICS3_MASK  (0x00000008u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS3_SHIFT (0x00000003u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS3_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICSR_ICS2_MASK  (0x00000004u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS2_SHIFT (0x00000002u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS2_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICSR_ICS1_MASK  (0x00000002u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS1_SHIFT (0x00000001u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS1_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICSR_ICS0_MASK  (0x00000001u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS0_SHIFT (0x00000000u)
#define CSL_SRIO_TX_CPPI_ICSR_ICS0_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICSR_RESETVAL   (0x00000000u)

/* TX_CPPI_ICCR */

#define CSL_SRIO_TX_CPPI_ICCR_ICC15_MASK (0x00008000u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC15_SHIFT (0x0000000Fu)
#define CSL_SRIO_TX_CPPI_ICCR_ICC15_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICCR_ICC14_MASK (0x00004000u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC14_SHIFT (0x0000000Eu)
#define CSL_SRIO_TX_CPPI_ICCR_ICC14_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICCR_ICC13_MASK (0x00002000u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC13_SHIFT (0x0000000Du)
#define CSL_SRIO_TX_CPPI_ICCR_ICC13_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICCR_ICC12_MASK (0x00001000u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC12_SHIFT (0x0000000Cu)
#define CSL_SRIO_TX_CPPI_ICCR_ICC12_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICCR_ICC11_MASK (0x00000800u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC11_SHIFT (0x0000000Bu)
#define CSL_SRIO_TX_CPPI_ICCR_ICC11_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICCR_ICC10_MASK (0x00000400u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC10_SHIFT (0x0000000Au)
#define CSL_SRIO_TX_CPPI_ICCR_ICC10_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICCR_ICC9_MASK  (0x00000200u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC9_SHIFT (0x00000009u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC9_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICCR_ICC8_MASK  (0x00000100u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC8_SHIFT (0x00000008u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC8_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICCR_ICC7_MASK  (0x00000080u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC7_SHIFT (0x00000007u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC7_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICCR_ICC6_MASK  (0x00000040u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC6_SHIFT (0x00000006u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC6_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICCR_ICC5_MASK  (0x00000020u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC5_SHIFT (0x00000005u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC5_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICCR_ICC4_MASK  (0x00000010u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC4_SHIFT (0x00000004u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC4_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICCR_ICC3_MASK  (0x00000008u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC3_SHIFT (0x00000003u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC3_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICCR_ICC2_MASK  (0x00000004u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC2_SHIFT (0x00000002u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC2_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICCR_ICC1_MASK  (0x00000002u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC1_SHIFT (0x00000001u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC1_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICCR_ICC0_MASK  (0x00000001u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC0_SHIFT (0x00000000u)
#define CSL_SRIO_TX_CPPI_ICCR_ICC0_RESETVAL (0x00000000u)

#define CSL_SRIO_TX_CPPI_ICCR_RESETVAL   (0x00000000u)

/* LSU_ICSR */

#define CSL_SRIO_LSU_ICSR_ICS31_MASK     (0x80000000u)
#define CSL_SRIO_LSU_ICSR_ICS31_SHIFT    (0x0000001Fu)
#define CSL_SRIO_LSU_ICSR_ICS31_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS30_MASK     (0x40000000u)
#define CSL_SRIO_LSU_ICSR_ICS30_SHIFT    (0x0000001Eu)
#define CSL_SRIO_LSU_ICSR_ICS30_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS29_MASK     (0x20000000u)
#define CSL_SRIO_LSU_ICSR_ICS29_SHIFT    (0x0000001Du)
#define CSL_SRIO_LSU_ICSR_ICS29_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS28_MASK     (0x10000000u)
#define CSL_SRIO_LSU_ICSR_ICS28_SHIFT    (0x0000001Cu)
#define CSL_SRIO_LSU_ICSR_ICS28_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS27_MASK     (0x08000000u)
#define CSL_SRIO_LSU_ICSR_ICS27_SHIFT    (0x0000001Bu)
#define CSL_SRIO_LSU_ICSR_ICS27_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS26_MASK     (0x04000000u)
#define CSL_SRIO_LSU_ICSR_ICS26_SHIFT    (0x0000001Au)
#define CSL_SRIO_LSU_ICSR_ICS26_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS25_MASK     (0x02000000u)
#define CSL_SRIO_LSU_ICSR_ICS25_SHIFT    (0x00000019u)
#define CSL_SRIO_LSU_ICSR_ICS25_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS24_MASK     (0x01000000u)
#define CSL_SRIO_LSU_ICSR_ICS24_SHIFT    (0x00000018u)
#define CSL_SRIO_LSU_ICSR_ICS24_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS23_MASK     (0x00800000u)
#define CSL_SRIO_LSU_ICSR_ICS23_SHIFT    (0x00000017u)
#define CSL_SRIO_LSU_ICSR_ICS23_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS22_MASK     (0x00400000u)
#define CSL_SRIO_LSU_ICSR_ICS22_SHIFT    (0x00000016u)
#define CSL_SRIO_LSU_ICSR_ICS22_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS21_MASK     (0x00200000u)
#define CSL_SRIO_LSU_ICSR_ICS21_SHIFT    (0x00000015u)
#define CSL_SRIO_LSU_ICSR_ICS21_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS20_MASK     (0x00100000u)
#define CSL_SRIO_LSU_ICSR_ICS20_SHIFT    (0x00000014u)
#define CSL_SRIO_LSU_ICSR_ICS20_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS19_MASK     (0x00080000u)
#define CSL_SRIO_LSU_ICSR_ICS19_SHIFT    (0x00000013u)
#define CSL_SRIO_LSU_ICSR_ICS19_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS18_MASK     (0x00040000u)
#define CSL_SRIO_LSU_ICSR_ICS18_SHIFT    (0x00000012u)
#define CSL_SRIO_LSU_ICSR_ICS18_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS17_MASK     (0x00020000u)
#define CSL_SRIO_LSU_ICSR_ICS17_SHIFT    (0x00000011u)
#define CSL_SRIO_LSU_ICSR_ICS17_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS16_MASK     (0x00010000u)
#define CSL_SRIO_LSU_ICSR_ICS16_SHIFT    (0x00000010u)
#define CSL_SRIO_LSU_ICSR_ICS16_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS15_MASK     (0x00008000u)
#define CSL_SRIO_LSU_ICSR_ICS15_SHIFT    (0x0000000Fu)
#define CSL_SRIO_LSU_ICSR_ICS15_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS14_MASK     (0x00004000u)
#define CSL_SRIO_LSU_ICSR_ICS14_SHIFT    (0x0000000Eu)
#define CSL_SRIO_LSU_ICSR_ICS14_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS13_MASK     (0x00002000u)
#define CSL_SRIO_LSU_ICSR_ICS13_SHIFT    (0x0000000Du)
#define CSL_SRIO_LSU_ICSR_ICS13_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS12_MASK     (0x00001000u)
#define CSL_SRIO_LSU_ICSR_ICS12_SHIFT    (0x0000000Cu)
#define CSL_SRIO_LSU_ICSR_ICS12_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS11_MASK     (0x00000800u)
#define CSL_SRIO_LSU_ICSR_ICS11_SHIFT    (0x0000000Bu)
#define CSL_SRIO_LSU_ICSR_ICS11_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS10_MASK     (0x00000400u)
#define CSL_SRIO_LSU_ICSR_ICS10_SHIFT    (0x0000000Au)
#define CSL_SRIO_LSU_ICSR_ICS10_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS9_MASK      (0x00000200u)
#define CSL_SRIO_LSU_ICSR_ICS9_SHIFT     (0x00000009u)
#define CSL_SRIO_LSU_ICSR_ICS9_RESETVAL  (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS8_MASK      (0x00000100u)
#define CSL_SRIO_LSU_ICSR_ICS8_SHIFT     (0x00000008u)
#define CSL_SRIO_LSU_ICSR_ICS8_RESETVAL  (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS7_MASK      (0x00000080u)
#define CSL_SRIO_LSU_ICSR_ICS7_SHIFT     (0x00000007u)
#define CSL_SRIO_LSU_ICSR_ICS7_RESETVAL  (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS6_MASK      (0x00000040u)
#define CSL_SRIO_LSU_ICSR_ICS6_SHIFT     (0x00000006u)
#define CSL_SRIO_LSU_ICSR_ICS6_RESETVAL  (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS5_MASK      (0x00000020u)
#define CSL_SRIO_LSU_ICSR_ICS5_SHIFT     (0x00000005u)
#define CSL_SRIO_LSU_ICSR_ICS5_RESETVAL  (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS4_MASK      (0x00000010u)
#define CSL_SRIO_LSU_ICSR_ICS4_SHIFT     (0x00000004u)
#define CSL_SRIO_LSU_ICSR_ICS4_RESETVAL  (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS3_MASK      (0x00000008u)
#define CSL_SRIO_LSU_ICSR_ICS3_SHIFT     (0x00000003u)
#define CSL_SRIO_LSU_ICSR_ICS3_RESETVAL  (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS2_MASK      (0x00000004u)
#define CSL_SRIO_LSU_ICSR_ICS2_SHIFT     (0x00000002u)
#define CSL_SRIO_LSU_ICSR_ICS2_RESETVAL  (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS1_MASK      (0x00000002u)
#define CSL_SRIO_LSU_ICSR_ICS1_SHIFT     (0x00000001u)
#define CSL_SRIO_LSU_ICSR_ICS1_RESETVAL  (0x00000000u)

#define CSL_SRIO_LSU_ICSR_ICS0_MASK      (0x00000001u)
#define CSL_SRIO_LSU_ICSR_ICS0_SHIFT     (0x00000000u)
#define CSL_SRIO_LSU_ICSR_ICS0_RESETVAL  (0x00000000u)

#define CSL_SRIO_LSU_ICSR_RESETVAL       (0x00000000u)

/* LSU_ICCR */

#define CSL_SRIO_LSU_ICCR_ICC31_MASK     (0x80000000u)
#define CSL_SRIO_LSU_ICCR_ICC31_SHIFT    (0x0000001Fu)
#define CSL_SRIO_LSU_ICCR_ICC31_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICCR_ICC30_MASK     (0x40000000u)
#define CSL_SRIO_LSU_ICCR_ICC30_SHIFT    (0x0000001Eu)
#define CSL_SRIO_LSU_ICCR_ICC30_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICCR_ICC29_MASK     (0x20000000u)
#define CSL_SRIO_LSU_ICCR_ICC29_SHIFT    (0x0000001Du)
#define CSL_SRIO_LSU_ICCR_ICC29_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICCR_ICC28_MASK     (0x10000000u)
#define CSL_SRIO_LSU_ICCR_ICC28_SHIFT    (0x0000001Cu)
#define CSL_SRIO_LSU_ICCR_ICC28_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICCR_ICC27_MASK     (0x08000000u)
#define CSL_SRIO_LSU_ICCR_ICC27_SHIFT    (0x0000001Bu)
#define CSL_SRIO_LSU_ICCR_ICC27_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICCR_ICC26_MASK     (0x04000000u)
#define CSL_SRIO_LSU_ICCR_ICC26_SHIFT    (0x0000001Au)
#define CSL_SRIO_LSU_ICCR_ICC26_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICCR_ICC25_MASK     (0x02000000u)
#define CSL_SRIO_LSU_ICCR_ICC25_SHIFT    (0x00000019u)
#define CSL_SRIO_LSU_ICCR_ICC25_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICCR_ICC24_MASK     (0x01000000u)
#define CSL_SRIO_LSU_ICCR_ICC24_SHIFT    (0x00000018u)
#define CSL_SRIO_LSU_ICCR_ICC24_RESETVAL (0x00000000u)

#define CSL_SRIO_LSU_ICCR_ICC23_MASK     (0x00800000u)
#define CSL_SRIO_LSU_ICCR_ICC23_SHIFT    (0x00000017u)