cslr_srio.h

Dm6455 driver,magbe useful to you!

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */
/** ============================================================================
 *   @file  cslr_srio.h
 *
 *   @path  $(CSLPATH)\inc
 *
 *   @desc  This file contains the Register Descriptions for SRIO
 */
#ifndef _CSLR_SRIO_H_
#define _CSLR_SRIO_H_

#include <cslr.h>
#include <tistdtypes.h>

/**************************************************************************\
* Register Overlay Structure for the Buffer Descriptors
\**************************************************************************/
typedef struct buffDesc {
    Uint32 nextDescPtr;
    Uint32 buffPtr;
    Uint32 opt1;
    Uint32 opt2;
} CSL_SrioBuffDesc;

/**************************************************************************\
* Register Overlay Structure for BLK_ENABLE 
\**************************************************************************/
typedef struct  {
    volatile Uint32 BLK_EN;
    volatile Uint32 BLK_EN_STAT;
} CSL_SrioBlk_enableRegs;

/**************************************************************************\
* Register Overlay Structure for HW_PKT_FWD 
\**************************************************************************/
typedef struct  {
    volatile Uint32 PF_16BIT_CNTL;
    volatile Uint32 PF_8BIT_CNTL;
} CSL_SrioHw_pkt_fwdRegs;

/**************************************************************************\
* Register Overlay Structure for DOORBELL_INTR 
\**************************************************************************/
typedef struct  {
    volatile Uint32 DOORBELL_ICSR;
    volatile Uint8 RSVD0[4];
    volatile Uint32 DOORBELL_ICCR;
    volatile Uint8 RSVD1[4];
} CSL_SrioDoorbell_intrRegs;

/**************************************************************************\
* Register Overlay Structure for DOORBELL_INTR_ROUTE 
\**************************************************************************/
typedef struct  {
    volatile Uint32 DOORBELL_ICRR;
    volatile Uint32 DOORBELL_ICRR2;
    volatile Uint8 RSVD0[8];
} CSL_SrioDoorbell_intr_routeRegs;

/**************************************************************************\
* Register Overlay Structure for LSU 
\**************************************************************************/
typedef struct  {
    volatile Uint32 LSU_REG0;
    volatile Uint32 LSU_REG1;
    volatile Uint32 LSU_REG2;
    volatile Uint32 LSU_REG3;
    volatile Uint32 LSU_REG4;
    volatile Uint32 LSU_REG5;
    volatile Uint32 LSU_REG6;
    volatile Uint32 LSU_FLOW_MASKS;
} CSL_SrioLsuRegs;

/**************************************************************************\
* Register Overlay Structure for MAP 
\**************************************************************************/
typedef struct  {
    volatile Uint32 RXU_MAP_L;
    volatile Uint32 RXU_MAP_H;
} CSL_SrioMapRegs;

/**************************************************************************\
* Register Overlay Structure for PORT 
\**************************************************************************/
typedef struct  {
    volatile Uint32 SP_LM_REQ;
    volatile Uint32 SP_LM_RESP;
    volatile Uint32 SP_ACKID_STAT;
    volatile Uint8 RSVD0[12];
    volatile Uint32 SP_ERR_STAT;
    volatile Uint32 SP_CTL;
} CSL_SrioPortRegs;

/**************************************************************************\
* Register Overlay Structure for PORT_ERROR 
\**************************************************************************/
typedef struct  {
    volatile Uint32 SP_ERR_DET;
    volatile Uint32 SP_RATE_EN;
    volatile Uint32 SP_ERR_ATTR_CAPT_DBG0;
    volatile Uint32 SP_ERR_CAPT_DBG[4];
    volatile Uint8 RSVD0[12];
    volatile Uint32 SP_ERR_RATE;
    volatile Uint32 SP_ERR_THRESH;
    volatile Uint8 RSVD1[16];
} CSL_SrioPort_errorRegs;

/**************************************************************************\
* Register Overlay Structure for PORT_OPTION 
\**************************************************************************/
typedef struct  {
    volatile Uint32 SP_RST_OPT;
    volatile Uint32 SP_CTL_INDEP;
    volatile Uint32 SP_SILENCE_TIMER;
    volatile Uint32 SP_MULT_EVNT_CS;
    volatile Uint8 RSVD0[4];
    volatile Uint32 SP_CS_TX;
    volatile Uint8 RSVD1[232];
} CSL_SrioPort_optionRegs;

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint32 PID;
    volatile Uint32 PCR;
    volatile Uint8 RSVD0[24];
    volatile Uint32 PER_SET_CNTL;
    volatile Uint8 RSVD1[12];
    volatile Uint32 GBL_EN;
    volatile Uint32 GBL_EN_STAT;
    CSL_SrioBlk_enableRegs BLK_ENABLE[9];
    volatile Uint32 DEVICEID_REG1;
    volatile Uint32 DEVICEID_REG2;
    volatile Uint8 RSVD3[8];
    CSL_SrioHw_pkt_fwdRegs HW_PKT_FWD[4];
    volatile Uint8 RSVD4[80];
    volatile Uint32 SERDES_CFGRX_CNTL[4];
    volatile Uint32 SERDES_CFGTX_CNTL[4];
    volatile Uint32 SERDES_CFG_CNTL[4];
    volatile Uint8 RSVD5[208];
    CSL_SrioDoorbell_intrRegs DOORBELL_INTR[4];
    volatile Uint32 RX_CPPI_ICSR;
    volatile Uint8 RSVD6[4];
    volatile Uint32 RX_CPPI_ICCR;
    volatile Uint8 RSVD7[4];
    volatile Uint32 TX_CPPI_ICSR;
    volatile Uint8 RSVD8[4];
    volatile Uint32 TX_CPPI_ICCR;
    volatile Uint8 RSVD9[4];
    volatile Uint32 LSU_ICSR;
    volatile Uint8 RSVD10[4];
    volatile Uint32 LSU_ICCR;
    volatile Uint8 RSVD11[4];
    volatile Uint32 ERR_RST_EVNT_ICSR;
    volatile Uint8 RSVD12[4];
    volatile Uint32 ERR_RST_EVNT_ICCR;
    volatile Uint8 RSVD13[4];
    CSL_SrioDoorbell_intr_routeRegs DOORBELL_INTR_ROUTE[4];
    volatile Uint32 RX_CPPI_ICRR;
    volatile Uint32 RX_CPPI_ICRR2;
    volatile Uint8 RSVD14[8];
    volatile Uint32 TX_CPPI_ICRR;
    volatile Uint32 TX_CPPI_ICRR2;
    volatile Uint8 RSVD15[8];
    volatile Uint32 LSU_ICRR[4];
    volatile Uint32 ERR_RST_EVNT_ICRR;
    volatile Uint32 ERR_RST_EVNT_ICRR2;
    volatile Uint32 ERR_RST_EVNT_ICRR3;
    volatile Uint8 RSVD16[4];
    volatile Uint32 INTDST_DECODE[8];
    volatile Uint32 INTDST_RATE_CNTL[8];
    volatile Uint8 RSVD17[192];
    CSL_SrioLsuRegs LSU[4];
    volatile Uint8 RSVD18[128];
    volatile Uint32 QUEUE_TXDMA_HDP[16];
    volatile Uint8 RSVD19[64];
    volatile Uint32 QUEUE_TXDMA_CP[16];
    volatile Uint8 RSVD20[64];
    volatile Uint32 QUEUE_RXDMA_HDP[16];
    volatile Uint8 RSVD21[64];
    volatile Uint32 QUEUE_RXDMA_CP[16];
    volatile Uint8 RSVD22[64];
    volatile Uint32 TX_QUEUE_TEAR_DOWN;
    volatile Uint32 TX_CPPI_FLOW_MASKS[8];
    volatile Uint8 RSVD23[28];
    volatile Uint32 RX_QUEUE_TEAR_DOWN;
    volatile Uint32 RX_CPPI_CNTL;
    volatile Uint8 RSVD24[152];
    volatile Uint32 TX_QUEUE_CNTL0;
    volatile Uint32 TX_QUEUE_CNTL1;
    volatile Uint32 TX_QUEUE_CNTL2;
    volatile Uint32 TX_QUEUE_CNTL3;
    volatile Uint8 RSVD25[16];
    CSL_SrioMapRegs MAP[32];
    volatile Uint32 FLOW_CNTL[16];
    volatile Uint8 RSVD27[1728];
    volatile Uint32 DEV_ID;
    volatile Uint32 DEV_INFO;
    volatile Uint32 ASBLY_ID;
    volatile Uint32 ASBLY_INFO;
    volatile Uint32 PE_FEAT;
    volatile Uint8 RSVD28[4];
    volatile Uint32 SRC_OP;
    volatile Uint32 DEST_OP;
    volatile Uint8 RSVD29[44];
    volatile Uint32 PE_LL_CTL;
    volatile Uint8 RSVD30[8];
    volatile Uint32 LCL_CFG_HBAR;
    volatile Uint32 LCL_CFG_BAR;
    volatile Uint32 BASE_ID;
    volatile Uint8 RSVD31[4];
    volatile Uint32 HOST_BASE_ID_LOCK;
    volatile Uint32 COMP_TAG;
    volatile Uint8 RSVD32[144];
    volatile Uint32 SP_MB_HEAD;
    volatile Uint8 RSVD33[28];
    volatile Uint32 SP_LT_CTL;
    volatile Uint32 SP_RT_CTL;
    volatile Uint8 RSVD34[20];
    volatile Uint32 SP_GEN_CTL;
    CSL_SrioPortRegs PORT[4];
    volatile Uint8 RSVD35[3648];
    volatile Uint32 ERR_RPT_BH;
    volatile Uint8 RSVD36[4];
    volatile Uint32 ERR_DET;
    volatile Uint32 ERR_EN;
    volatile Uint32 H_ADDR_CAPT;
    volatile Uint32 ADDR_CAPT;
    volatile Uint32 ID_CAPT;
    volatile Uint32 CTRL_CAPT;
    volatile Uint8 RSVD37[8];
    volatile Uint32 PW_TGT_ID;
    volatile Uint8 RSVD38[20];
    CSL_SrioPort_errorRegs PORT_ERROR[4];
    volatile Uint8 RSVD39[65216];
    volatile Uint32 SP_IP_DISCOVERY_TIMER;
    volatile Uint32 SP_IP_MODE;
    volatile Uint32 IP_PRESCAL;
    volatile Uint8 RSVD40[4];
    volatile Uint32 SP_IP_PW_IN_CAPT[4];
    volatile Uint8 RSVD41[8160];
    CSL_SrioPort_optionRegs PORT_OPTION[4];
    volatile Uint8 RSVD42[965864];
    CSL_SrioBuffDesc txBuffDesc[32];
    CSL_SrioBuffDesc rxBuffDesc[32];
} CSL_SrioRegs;

/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_SrioRegs             *CSL_SrioRegsOvly;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* PID */

#define CSL_SRIO_PID_TYPE_MASK           (0x00FF0000u)
#define CSL_SRIO_PID_TYPE_SHIFT          (0x00000010u)
#define CSL_SRIO_PID_TYPE_RESETVAL       (0x00000001u)

#define CSL_SRIO_PID_CLASS_MASK          (0x0000FF00u)
#define CSL_SRIO_PID_CLASS_SHIFT         (0x00000008u)
#define CSL_SRIO_PID_CLASS_RESETVAL      (0x0000000Au)

#define CSL_SRIO_PID_REV_MASK            (0x000000FFu)
#define CSL_SRIO_PID_REV_SHIFT           (0x00000000u)
#define CSL_SRIO_PID_REV_RESETVAL        (0x00000001u)

#define CSL_SRIO_PID_RESETVAL            (0x00010A01u)

/* PCR */

#define CSL_SRIO_PCR_PEREN_MASK          (0x00000004u)
#define CSL_SRIO_PCR_PEREN_SHIFT         (0x00000002u)
#define CSL_SRIO_PCR_PEREN_RESETVAL      (0x00000000u)

/*----PEREN Tokens----*/
#define CSL_SRIO_PCR_PEREN_DISABLE       (0x00000000u)
#define CSL_SRIO_PCR_PEREN_ENABLE        (0x00000001u)

#define CSL_SRIO_PCR_SOFT_MASK           (0x00000002u)
#define CSL_SRIO_PCR_SOFT_SHIFT          (0x00000001u)
#define CSL_SRIO_PCR_SOFT_RESETVAL       (0x00000000u)

#define CSL_SRIO_PCR_FREE_MASK           (0x00000001u)
#define CSL_SRIO_PCR_FREE_SHIFT          (0x00000000u)
#define CSL_SRIO_PCR_FREE_RESETVAL       (0x00000001u)

#define CSL_SRIO_PCR_RESETVAL            (0x00000001u)

/* PER_SET_CNTL */

#define CSL_SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE_MASK (0x04000000u)
#define CSL_SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE_SHIFT (0x0000001Au)
#define CSL_SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE_RESETVAL (0x00000001u)

/*----SW_MEM_SLEEP_OVERRIDE Tokens----*/
#define CSL_SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE_DISABLE (0x00000000u)
#define CSL_SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE_ENABLE (0x00000001u)

#define CSL_SRIO_PER_SET_CNTL_LOOPBACK_MASK (0x02000000u)
#define CSL_SRIO_PER_SET_CNTL_LOOPBACK_SHIFT (0x00000019u)
#define CSL_SRIO_PER_SET_CNTL_LOOPBACK_RESETVAL (0x00000000u)

/*----LOOPBACK Tokens----*/
#define CSL_SRIO_PER_SET_CNTL_LOOPBACK_NORMAL (0x00000000u)
#define CSL_SRIO_PER_SET_CNTL_LOOPBACK_LOOPBACK (0x00000001u)

#define CSL_SRIO_PER_SET_CNTL_BOOT_COMPLETE_MASK (0x01000000u)