cslr_dev.h

Dm6455 driver,magbe useful to you!

#define CSL_DEV_PERCFG0_MCBSP1CTL_MASK   (0x00010000u)
#define CSL_DEV_PERCFG0_MCBSP1CTL_SHIFT  (0x00000010u)
#define CSL_DEV_PERCFG0_MCBSP1CTL_RESETVAL (0x00000000u)

/*----MCBSP1CTL Tokens----*/
#define CSL_DEV_PERCFG0_MCBSP1CTL_ENABLE (0x00000001u)

#define CSL_DEV_PERCFG0_MCBSP0CTL_MASK   (0x00004000u)
#define CSL_DEV_PERCFG0_MCBSP0CTL_SHIFT  (0x0000000Eu)
#define CSL_DEV_PERCFG0_MCBSP0CTL_RESETVAL (0x00000000u)

/*----MCBSP0CTL Tokens----*/
#define CSL_DEV_PERCFG0_MCBSP0CTL_ENABLE (0x00000001u)

#define CSL_DEV_PERCFG0_I2CCTL_MASK      (0x00001000u)
#define CSL_DEV_PERCFG0_I2CCTL_SHIFT     (0x0000000Cu)
#define CSL_DEV_PERCFG0_I2CCTL_RESETVAL  (0x00000000u)

/*----I2CCTL Tokens----*/
#define CSL_DEV_PERCFG0_I2CCTL_ENABLE    (0x00000001u)

#define CSL_DEV_PERCFG0_GPIOCTL_MASK     (0x00000400u)
#define CSL_DEV_PERCFG0_GPIOCTL_SHIFT    (0x0000000Au)
#define CSL_DEV_PERCFG0_GPIOCTL_RESETVAL (0x00000000u)

/*----GPIOCTL Tokens----*/
#define CSL_DEV_PERCFG0_GPIOCTL_ENABLE   (0x00000001u)

#define CSL_DEV_PERCFG0_TIMER1CTL_MASK   (0x00000100u)
#define CSL_DEV_PERCFG0_TIMER1CTL_SHIFT  (0x00000008u)
#define CSL_DEV_PERCFG0_TIMER1CTL_RESETVAL (0x00000000u)

/*----TIMER1CTL Tokens----*/
#define CSL_DEV_PERCFG0_TIMER1CTL_ENABLE (0x00000001u)

#define CSL_DEV_PERCFG0_TIMER0CTL_MASK   (0x00000040u)
#define CSL_DEV_PERCFG0_TIMER0CTL_SHIFT  (0x00000006u)
#define CSL_DEV_PERCFG0_TIMER0CTL_RESETVAL (0x00000000u)

/*----TIMER0CTL Tokens----*/
#define CSL_DEV_PERCFG0_TIMER0CTL_ENABLE (0x00000001u)

#define CSL_DEV_PERCFG0_EMACCTL_MASK     (0x00000010u)
#define CSL_DEV_PERCFG0_EMACCTL_SHIFT    (0x00000004u)
#define CSL_DEV_PERCFG0_EMACCTL_RESETVAL (0x00000000u)

/*----EMACCTL Tokens----*/
#define CSL_DEV_PERCFG0_EMACCTL_ENABLE   (0x00000001u)

#define CSL_DEV_PERCFG0_VCPCTL_MASK      (0x00000004u)
#define CSL_DEV_PERCFG0_VCPCTL_SHIFT     (0x00000002u)
#define CSL_DEV_PERCFG0_VCPCTL_RESETVAL  (0x00000000u)

/*----VCPCTL Tokens----*/
#define CSL_DEV_PERCFG0_VCPCTL_ENABLE    (0x00000001u)

#define CSL_DEV_PERCFG0_TCPCTL_MASK      (0x00000001u)
#define CSL_DEV_PERCFG0_TCPCTL_SHIFT     (0x00000000u)
#define CSL_DEV_PERCFG0_TCPCTL_RESETVAL  (0x00000000u)

/*----TCPCTL Tokens----*/
#define CSL_DEV_PERCFG0_TCPCTL_ENABLE    (0x00000001u)

#define CSL_DEV_PERCFG0_RESETVAL         (0x00000000u)

/* PERSTAT0 */

#define CSL_DEV_PERSTAT0_HPISTAT_MASK    (0x38000000u)
#define CSL_DEV_PERSTAT0_HPISTAT_SHIFT   (0x0000001Bu)
#define CSL_DEV_PERSTAT0_HPISTAT_RESETVAL (0x00000000u)

/*----HPISTAT Tokens----*/
#define CSL_DEV_PERSTAT0_HPISTAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_HPISTAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_HPISTAT_ENABLE  (0x00000001u)
#define CSL_DEV_PERSTAT0_HPISTAT_ENABLE_IN_PROGRESS (0x00000005u)

#define CSL_DEV_PERSTAT0_MCBSP1STAT_MASK (0x07000000u)
#define CSL_DEV_PERSTAT0_MCBSP1STAT_SHIFT (0x00000018u)
#define CSL_DEV_PERSTAT0_MCBSP1STAT_RESETVAL (0x00000000u)

/*----MCBSP1STAT Tokens----*/
#define CSL_DEV_PERSTAT0_MCBSP1STAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_MCBSP1STAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_MCBSP1STAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT0_MCBSP1STAT_ENABLE_IN_PROGRESS (0x00000005u)

#define CSL_DEV_PERSTAT0_MCBSP0STAT_MASK (0x00E00000u)
#define CSL_DEV_PERSTAT0_MCBSP0STAT_SHIFT (0x00000015u)
#define CSL_DEV_PERSTAT0_MCBSP0STAT_RESETVAL (0x00000000u)

/*----MCBSP0STAT Tokens----*/
#define CSL_DEV_PERSTAT0_MCBSP0STAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_MCBSP0STAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_MCBSP0STAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT0_MCBSP0STAT_ENABLE_IN_PROGRESS (0x00000005u)

#define CSL_DEV_PERSTAT0_I2CSTAT_MASK    (0x001C0000u)
#define CSL_DEV_PERSTAT0_I2CSTAT_SHIFT   (0x00000012u)
#define CSL_DEV_PERSTAT0_I2CSTAT_RESETVAL (0x00000000u)

/*----I2CSTAT Tokens----*/
#define CSL_DEV_PERSTAT0_I2CSTAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_I2CSTAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_I2CSTAT_ENABLE  (0x00000001u)
#define CSL_DEV_PERSTAT0_I2CSTAT_ENABLE_IN_PROGRESS (0x00000005u)

#define CSL_DEV_PERSTAT0_GPIOSTAT_MASK   (0x00038000u)
#define CSL_DEV_PERSTAT0_GPIOSTAT_SHIFT  (0x0000000Fu)
#define CSL_DEV_PERSTAT0_GPIOSTAT_RESETVAL (0x00000000u)

/*----GPIOSTAT Tokens----*/
#define CSL_DEV_PERSTAT0_GPIOSTAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_GPIOSTAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_GPIOSTAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT0_GPIOSTAT_ENABLE_IN_PROGRESS (0x00000005u)

#define CSL_DEV_PERSTAT0_TIMER1STAT_MASK (0x00007000u)
#define CSL_DEV_PERSTAT0_TIMER1STAT_SHIFT (0x0000000Cu)
#define CSL_DEV_PERSTAT0_TIMER1STAT_RESETVAL (0x00000000u)

/*----TIMER1STAT Tokens----*/
#define CSL_DEV_PERSTAT0_TIMER1STAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_TIMER1STAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_TIMER1STAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT0_TIMER1STAT_ENABLE_IN_PROGRESS (0x00000005u)

#define CSL_DEV_PERSTAT0_TIMER0STAT_MASK (0x00000E00u)
#define CSL_DEV_PERSTAT0_TIMER0STAT_SHIFT (0x00000009u)
#define CSL_DEV_PERSTAT0_TIMER0STAT_RESETVAL (0x00000000u)

/*----TIMER0STAT Tokens----*/
#define CSL_DEV_PERSTAT0_TIMER0STAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_TIMER0STAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_TIMER0STAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT0_TIMER0STAT_ENABLE_IN_PROGRESS (0x00000005u)

#define CSL_DEV_PERSTAT0_EMACSTAT_MASK   (0x000001C0u)
#define CSL_DEV_PERSTAT0_EMACSTAT_SHIFT  (0x00000006u)
#define CSL_DEV_PERSTAT0_EMACSTAT_RESETVAL (0x00000000u)

/*----EMACSTAT Tokens----*/
#define CSL_DEV_PERSTAT0_EMACSTAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_EMACSTAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_EMACSTAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT0_EMACSTAT_ENABLE_IN_PROGRESS (0x00000005u)

#define CSL_DEV_PERSTAT0_VCPSTAT_MASK    (0x00000038u)
#define CSL_DEV_PERSTAT0_VCPSTAT_SHIFT   (0x00000003u)
#define CSL_DEV_PERSTAT0_VCPSTAT_RESETVAL (0x00000000u)

/*----VCPSTAT Tokens----*/
#define CSL_DEV_PERSTAT0_VCPSTAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_VCPSTAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_VCPSTAT_ENABLE  (0x00000001u)
#define CSL_DEV_PERSTAT0_VCPSTAT_ENABLE_IN_PROGRESS (0x00000005u)

#define CSL_DEV_PERSTAT0_TCPSTAT_MASK    (0x00000007u)
#define CSL_DEV_PERSTAT0_TCPSTAT_SHIFT   (0x00000000u)
#define CSL_DEV_PERSTAT0_TCPSTAT_RESETVAL (0x00000000u)

/*----TCPSTAT Tokens----*/
#define CSL_DEV_PERSTAT0_TCPSTAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT0_TCPSTAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT0_TCPSTAT_ENABLE  (0x00000001u)
#define CSL_DEV_PERSTAT0_TCPSTAT_ENABLE_IN_PROGRESS (0x00000005u)

#define CSL_DEV_PERSTAT0_RESETVAL        (0x00000000u)

/* PERSTAT1 */

#define CSL_DEV_PERSTAT1_UTOPIASTAT_MASK (0x00000038u)
#define CSL_DEV_PERSTAT1_UTOPIASTAT_SHIFT (0x00000003u)
#define CSL_DEV_PERSTAT1_UTOPIASTAT_RESETVAL (0x00000000u)

/*----UTOPIASTAT Tokens----*/
#define CSL_DEV_PERSTAT1_UTOPIASTAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT1_UTOPIASTAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT1_UTOPIASTAT_ENABLE (0x00000001u)
#define CSL_DEV_PERSTAT1_UTOPIASTAT_ENABLE_IN_PROGRESS (0x00000005u)

#define CSL_DEV_PERSTAT1_PCISTAT_MASK    (0x00000007u)
#define CSL_DEV_PERSTAT1_PCISTAT_SHIFT   (0x00000000u)
#define CSL_DEV_PERSTAT1_PCISTAT_RESETVAL (0x00000000u)

/*----PCISTAT Tokens----*/
#define CSL_DEV_PERSTAT1_PCISTAT_STATIC_PDN (0x00000003u)
#define CSL_DEV_PERSTAT1_PCISTAT_DISABLE (0x00000000u)
#define CSL_DEV_PERSTAT1_PCISTAT_ENABLE  (0x00000001u)
#define CSL_DEV_PERSTAT1_PCISTAT_ENABLE_IN_PROGRESS (0x00000005u)

#define CSL_DEV_PERSTAT1_RESETVAL        (0x00000000u)

/* EMACCFG */

#define CSL_DEV_EMACCFG_RMII_RST_MASK    (0x00080000u)
#define CSL_DEV_EMACCFG_RMII_RST_SHIFT   (0x00000013u)
#define CSL_DEV_EMACCFG_RMII_RST_RESETVAL (0x00000001u)

/*----RMII_RST Tokens----*/
#define CSL_DEV_EMACCFG_RMII_RST_ASSERT  (0x00000000u)
#define CSL_DEV_EMACCFG_RMII_RST_RELEASE (0x00000001u)

#define CSL_DEV_EMACCFG_RESETVAL         (0x00080000u)

/* PERCFG1 */

#define CSL_DEV_PERCFG1_DDR2CTL_MASK     (0x00000002u)
#define CSL_DEV_PERCFG1_DDR2CTL_SHIFT    (0x00000001u)
#define CSL_DEV_PERCFG1_DDR2CTL_RESETVAL (0x00000000u)

/*----DDR2CTL Tokens----*/
#define CSL_DEV_PERCFG1_DDR2CTL_ENABLE   (0x00000001u)

#define CSL_DEV_PERCFG1_EMIFACTL_MASK    (0x00000001u)
#define CSL_DEV_PERCFG1_EMIFACTL_SHIFT   (0x00000000u)
#define CSL_DEV_PERCFG1_EMIFACTL_RESETVAL (0x00000000u)

/*----EMIFACTL Tokens----*/
#define CSL_DEV_PERCFG1_EMIFACTL_ENABLE  (0x00000001u)

#define CSL_DEV_PERCFG1_RESETVAL         (0x00000000u)

/* EMUBUFPDN */

#define CSL_DEV_EMUBUFPDN_EMUCTL_MASK    (0x00000001u)
#define CSL_DEV_EMUBUFPDN_EMUCTL_SHIFT   (0x00000000u)
#define CSL_DEV_EMUBUFPDN_EMUCTL_RESETVAL (0x00000000u)

/*----EMUCTL Tokens----*/
#define CSL_DEV_EMUBUFPDN_EMUCTL_ENABLE  (0x00000000u)
#define CSL_DEV_EMUBUFPDN_EMUCTL_DISABLE (0x00000001u)

#define CSL_DEV_EMUBUFPDN_RESETVAL       (0x00000000u)

#endif