soc.h

Dm6455 driver,magbe useful to you!

#define    CSL_INTC_EVENTID_RINT0           (40)        
/* McBSP0 transmit interrupt */
#define    CSL_INTC_EVENTID_XINT0           (41)        
/* McBSP1 receive interrupt */
#define    CSL_INTC_EVENTID_RINT1           (42)        
/* McBSP1 transmit interrupt */
#define    CSL_INTC_EVENTID_XINT1           (43)        

/* Event ID 44-49 is reserved */ 

/* VLYNQ Pulse Interrupt    */
#define    CSL_INTC_EVENTID_VINT            (50)        
/* GPIO Interrupt           */ 
#define    CSL_INTC_EVENTID_GPINT0          (51)         
/* GPIO Interrupt           */ 
#define    CSL_INTC_EVENTID_GPINT1          (52)        
/* GPIO Interrupt           */ 
#define    CSL_INTC_EVENTID_GPINT2          (53)        
/* GPIO Interrupt           */ 
#define    CSL_INTC_EVENTID_GPINT3          (54)        
/* GPIO Interrupt */
#define    CSL_INTC_EVENTID_GPINT4          (55)        
/* GPIO Interrupt */
#define    CSL_INTC_EVENTID_GPINT5          (56)        
/* GPIO Interrupt */
#define    CSL_INTC_EVENTID_GPINT6          (57)        
/* GPIO Interrupt */
#define    CSL_INTC_EVENTID_GPINT7          (58)        
/* GPIO Interrupt           */ 
#define    CSL_INTC_EVENTID_GPINT8          (59)        
/* GPIO Interrupt           */ 
#define    CSL_INTC_EVENTID_GPINT9          (60)        
/* GPIO Interrupt           */ 
#define    CSL_INTC_EVENTID_GPINT10         (61)        
/* GPIO Interrupt           */ 
#define    CSL_INTC_EVENTID_GPINT11         (62)        
/* GPIO Interrupt           */ 
#define    CSL_INTC_EVENTID_GPINT12         (63)        
/* GPIO Interrupt           */ 
#define    CSL_INTC_EVENTID_GPINT13         (64)        
/* GPIO Interrupt           */ 
#define    CSL_INTC_EVENTID_GPINT14         (65)        
/* GPIO Interrupt           */ 
#define    CSL_INTC_EVENTID_GPINT15         (66)        
/* Timer 0 lower counter interrupt     */
#define    CSL_INTC_EVENTID_TINTLO0         (67)        
/* Timer 0 higher counter interrupt    */
#define    CSL_INTC_EVENTID_TINTHI0         (68)        
/* Timer 1 lower counter interrupt     */
#define    CSL_INTC_EVENTID_TINTLO1         (69)        
/* Timer 1 higher counter interrupt    */
#define    CSL_INTC_EVENTID_TINTHI1         (70)        
/* CC Completion Interrupt - Mask0 */
#define    CSL_INTC_EVENTID_EDMA3CC_INT0       (71)        
/* CC Completion Interrupt - Mask1 */
#define    CSL_INTC_EVENTID_EDMA3CC_INT1       (72)        
/* CC Completion Interrupt - Mask2 */
#define    CSL_INTC_EVENTID_EDMA3CC_INT2       (73)        
/* CC Completion Interrupt - Mask3 */
#define    CSL_INTC_EVENTID_EDMA3CC_INT3       (74)        
/* CC Completion Interrupt - Mask4 */
#define    CSL_INTC_EVENTID_EDMA3CC_INT4       (75)        
/* CC Completion Interrupt - Mask5 */
#define    CSL_INTC_EVENTID_EDMA3CC_INT5       (76)        
/* CC Completion Interrupt - Mask6 */
#define    CSL_INTC_EVENTID_EDMA3CC_INT6       (77)        
/* CC Completion Interrupt - Mask7 */
#define    CSL_INTC_EVENTID_EDMA3CC_INT7       (78)        
/* CC Error Interrupt    */
#define    CSL_INTC_EVENTID_EDMA3CC_ERRINT     (79)              
/* CC Memory Protection Interrupt */
#define    CSL_INTC_EVENTID_EDMA3CC_MPINT      (80)        
/* TC0 Error Interrupt */
#define    CSL_INTC_EVENTID_EDMA3TC0_ERRINT    (81)        
/* TC1 Error Interrupt */
#define    CSL_INTC_EVENTID_EDMA3TC1_ERRINT    (82)        
/* TC2 Error Interrupt */
#define    CSL_INTC_EVENTID_EDMA3TC2_ERRINT    (83)        
/* TC3 Error Interrupt */
#define    CSL_INTC_EVENTID_EDMA3TC3_ERRINT    (84)        
 
/* Event ID 85-95 is reserved */ 

/* Dropped CPU interrupt event */
#define    CSL_INTC_EVENTID_INTERR          (96)        
/* EMC Invalid IDMA parameters     */
#define    CSL_INTC_EVENTID_EMC_IDMAERR     (97)           

/* Event ID 98 - 99 is reserved */ 

/* EFI Interrupt from side A    */
#define    CSL_INTC_EVENTID_EFIINTA         (100)       
/* EFI Interrupt from side B    */
#define    CSL_INTC_EVENTID_EFIINTB         (101)       

/* Event ID 102-112 is reserved */ 

/* L1P Single bit error detected during DMA read */
#define    CSL_INTC_EVENTID_L1P_ED1         (113)       

/* Event ID 114-115 is reserved */ 

/* L2 single bit error detected */
#define    CSL_INTC_EVENTID_L2_ED1         (116)       
/* L2 two bit error detected */
#define    CSL_INTC_EVENTID_L2_ED2         (117)       
/* Power Down sleep interrupt */
#define    CSL_INTC_EVENTID_PDC_INT        (118)       

/* Event ID 119 is reserved */ 

/* L1P CPU memory protection fault */
#define    CSL_INTC_EVENTID_L1P_CMPA        (120)       
/* L1P DMA memory protection fault */
#define    CSL_INTC_EVENTID_L1P_DMPA        (121)        
/* L1D CPU memory protection fault */
#define    CSL_INTC_EVENTID_L1D_CMPA        (122)       
/* L1D DMA memory protection fault */
#define    CSL_INTC_EVENTID_L1D_DMPA        (123)       
/* L2 CPU memory protection fault */
#define    CSL_INTC_EVENTID_L2_CMPA         (124)       
/* L2 DMA memory protection fault */
#define    CSL_INTC_EVENTID_L2_DMPA         (125)       
/* IDMA CPU memory protection fault */
#define    CSL_INTC_EVENTID_IDMA_CMPA       (126)       
/* IDMA Bus error interrupt  */
#define    CSL_INTC_EVENTID_IDMA_BUSERR     (127)       




/**** EDMA RELATED DEFINES  *********/


/**************************************************************************\
*  Parameterizable Configuration:- These are fed directly from the RTL
*  parameters for the given SOC
\**************************************************************************/

#define CSL_EDMA3_NUM_DMACH            64
#define CSL_EDMA3_NUM_QDMACH            4
#define CSL_EDMA3_NUM_PARAMSETS       256
#define CSL_EDMA3_NUM_EVQUE             4
#define CSL_EDMA3_CHMAPEXIST            1
#define CSL_EDMA3_NUM_REGIONS           8
#define CSL_EDMA3_MEMPROTECT            1

/**************************************************************************\
* Channel Instance count
\**************************************************************************/
#define CSL_EDMA3_CHA_CNT              68

/* EDMA channel synchronization events */
  
/* HPI/PCI-to-DSP event          */
#define CSL_EDMA3_CHA_DSP_EVT   0
/* Timer 0 lower counter event   */
#define CSL_EDMA3_CHA_TEVTLO0   1
/* Timer 0 higher counter event  */
#define CSL_EDMA3_CHA_TEVTHI0   2
/* EDMA3 channel 3 */
#define CSL_EDMA3_CHA_3         3
/* EDMA3 channel 4 */
#define CSL_EDMA3_CHA_4         4
/* EDMA3 channel 5 */
#define CSL_EDMA3_CHA_5         5
/* EDMA3 channel 6 */
#define CSL_EDMA3_CHA_6         6
/* EDMA3 channel 7 */
#define CSL_EDMA3_CHA_7         7
/* EDMA3 channel 8 */
#define CSL_EDMA3_CHA_8         8
/* EDMA3 channel 9 */
#define CSL_EDMA3_CHA_9         9
/* EDMA3 channel 10 */
#define CSL_EDMA3_CHA_10       10
/* EDMA3 channel 11 */
#define CSL_EDMA3_CHA_11       11
/* McBSP0 transmit event */
#define CSL_EDMA3_CHA_XEVT0    12
/* McBSP0 receive event  */
#define CSL_EDMA3_CHA_REVT0    13
/* McBSP1 transmit event */
#define CSL_EDMA3_CHA_XEVT1    14
/* McBSP1 receive event  */
#define CSL_EDMA3_CHA_REVT1    15
/* Timer 1 lower counter event  */
#define CSL_EDMA3_CHA_TEVTLO1   16
/* Timer 1 higher counter event */
#define CSL_EDMA3_CHA_TEVTHI1   17
/* EDMA channel 18*/
#define CSL_EDMA3_CHA_18       18
/* EDMA3 channel 19*/
#define CSL_EDMA3_CHA_19       19
/* Rapid IO Interrupt 1 */
#define CSL_EDMA3_CHA_RIOINT1  20
/* EDMA3 channel 21*/
#define CSL_EDMA3_CHA_21       21
/* EDMA3 channel 22*/
#define CSL_EDMA3_CHA_22       22
/* EDMA3 channel 23*/
#define CSL_EDMA3_CHA_23       23
/* EDMA3 channel 24*/
#define CSL_EDMA3_CHA_24       24
/* EDMA3 channel 25*/
#define CSL_EDMA3_CHA_25       25
/* EDMA3 channel 26*/
#define CSL_EDMA3_CHA_26       26
/* EDMA3 channel 27*/
#define CSL_EDMA3_CHA_27       27
/* VCP2 receive event  */
#define CSL_EDMA3_CHA_VCP2REVT  28
/* VCP2 transmit event */
#define CSL_EDMA3_CHA_VCP2XEVT  29
/* TCP2 receive event  */
#define CSL_EDMA3_CHA_TCP2REVT  30
/* TCP2 transmit event */
#define CSL_EDMA3_CHA_TCP2XEVT  31
/* UTOPIA receive event */
#define CSL_EDMA3_CHA_UREVT    32
/* EDMA3 channel 33 */
#define CSL_EDMA3_CHA_33       33
/* EDMA3 channel 34 */
#define CSL_EDMA3_CHA_34       34
/* EDMA3 channel 35 */
#define CSL_EDMA3_CHA_35       35
/* EDMA3 channel 36 */
#define CSL_EDMA3_CHA_36       36
/* EDMA3 channel 37 */
#define CSL_EDMA3_CHA_37       37
/* EDMA3 channel 38 */
#define CSL_EDMA3_CHA_38       38
/* EDMA3 channel 39 */
#define CSL_EDMA3_CHA_39       39
/* UTOPIA transmit event */
#define CSL_EDMA3_CHA_UXEVT    40
/* EDMA3 channel 41*/
#define CSL_EDMA3_CHA_41       41
/* EDMA3 channel 42*/
#define CSL_EDMA3_CHA_42       42
/* EDMA3 channel 43*/
#define CSL_EDMA3_CHA_43       43
/* I2C receive event */
#define CSL_EDMA3_CHA_ICREVT   44
/* I2C transmit event */
#define CSL_EDMA3_CHA_ICXEVT   45
/** EDMA3 channel 46*/
#define CSL_EDMA3_CHA_46       46
/** EDMA3 channel 47*/
#define CSL_EDMA3_CHA_47       47
/* GPIO event 0 */
#define CSL_EDMA3_CHA_GPINT0   48
/* GPIO event 1 */
#define CSL_EDMA3_CHA_GPINT1   49
/* GPIO event 2 */
#define CSL_EDMA3_CHA_GPINT2   50
/* GPIO event 3 */
#define CSL_EDMA3_CHA_GPINT3   51
/* GPIO event 4 */
#define CSL_EDMA3_CHA_GPINT4   52
/* GPIO event 5 */
#define CSL_EDMA3_CHA_GPINT5   53
/* GPIO event 6 */
#define CSL_EDMA3_CHA_GPINT6   54
/* GPIO event 7 */
#define CSL_EDMA3_CHA_GPINT7   55
/* GPIO event 8 */
#define CSL_EDMA3_CHA_GPINT8   56
/* GPIO event 9 */
#define CSL_EDMA3_CHA_GPINT9   57
/* GPIO event 10 */
#define CSL_EDMA3_CHA_GPINT10  58
/* GPIO event 11 */
#define CSL_EDMA3_CHA_GPINT11  59
/* GPIO event 12 */
#define CSL_EDMA3_CHA_GPINT12  60
/* GPIO event 13 */
#define CSL_EDMA3_CHA_GPINT13  61
/* GPIO event 14 */
#define CSL_EDMA3_CHA_GPINT14  62
/* GPIO event 15 */
#define CSL_EDMA3_CHA_GPINT15  63

/* QDMA channels */
#define    CSL_EDMA3_QCHA_0                     64   /* QDMA Channel 0*/
#define    CSL_EDMA3_QCHA_1                     65   /* QDMA Channel 1*/
#define    CSL_EDMA3_QCHA_2                     66   /* QDMA Channel 2*/
#define    CSL_EDMA3_QCHA_3                     67   /* QDMA Channel 3*/


/* Enumerations for EDMA Event Queues */
typedef enum {
	CSL_EDMA3_QUE_0 		   = 			   0, /* Queue 0 */  
	CSL_EDMA3_QUE_1 		   = 			   1, /* Queue 1 */  
	CSL_EDMA3_QUE_2 		   = 			   2, /* Queue 2 */  
	CSL_EDMA3_QUE_3 		   = 			   3  /* Queue 3 */  
} CSL_Edma3Que;

/* Enumerations for EDMA Transfer Controllers
 *
 * There are 4 Transfer Controllers. Typically a one to one mapping exists
 * between Event Queues and Transfer Controllers.
 *
 */
typedef enum {
	CSL_EDMA3_TC_0 		   = 			   0, /* TC 0 */  
	CSL_EDMA3_TC_1 		   = 			   1, /* TC 1 */  
	CSL_EDMA3_TC_2 		   = 			   2, /* TC 2 */  
	CSL_EDMA3_TC_3 		   = 			   3  /* TC 3 */  
} CSL_Edma3Tc;

#define CSL_EDMA3_REGION_GLOBAL  -1
#define CSL_EDMA3_REGION_0  0
#define CSL_EDMA3_REGION_1  1
#define CSL_EDMA3_REGION_2  2
#define CSL_EDMA3_REGION_3  3
#define CSL_EDMA3_REGION_4  4
#define CSL_EDMA3_REGION_5  5
#define CSL_EDMA3_REGION_6  6
#define CSL_EDMA3_REGION_7  7



/*********** DAT RELATED DEFINES ******************/

/**************************************************************************\
*  Parameterizable Configuration:- These are fed directly from the RTL 
*  parameters for the given SOC
\**************************************************************************/
/**************************************************************************\
* Channel Instance count
\**************************************************************************/
/** @brief Number of Generic Channel instances */


/** @brief Enumerations for EDMA channels
*
*  There are 4 QDMA channels -
*
*/

#define    CSL_DAT_QCHA_0		   		      0 /**< QDMA Channel 0*/
#define    CSL_DAT_QCHA_1		   		      1 /**< QDMA Channel 1*/
#define    CSL_DAT_QCHA_2    	   		      2 /**< QDMA Channel 2*/
#define    CSL_DAT_QCHA_3		   		      3 /**< QDMA Channel 3*/

/** @brief Enumerations for EDMA Event Queues
*
*  There are 4 Event Queues. Q0 is the highest priority and Q3 is the least priority
*
*/
typedef enum {
	CSL_DAT_PRI_DEFAULT   = 			   0, /* Queue 0 is default */  
	CSL_DAT_PRI_0 		   = 			   0, /* Queue 0 */  
	CSL_DAT_PRI_1 		   = 			   1, /* Queue 1 */  
	CSL_DAT_PRI_2 		   = 			   2, /* Queue 2 */  
	CSL_DAT_PRI_3 		   = 			   3  /* Queue 3 */  
} CSL_DatPriority;

/** @brief Enumeration for EDMA Regions 
*
*  
*/

#define	CSL_DAT_REGION_GLOBAL  -1  /* Global Region */
#define	CSL_DAT_REGION_0  0         /* EDMA Region 0 */
#define	CSL_DAT_REGION_1  1         /* EDMA Region 1 */
#define	CSL_DAT_REGION_2  2         /* EDMA Region 2 */
#define	CSL_DAT_REGION_3  3         /* EDMA Region 3 */
#define	CSL_DAT_REGION_4  4         /* EDMA Region 4 */
#define	CSL_DAT_REGION_5  5         /* EDMA Region 5 */
#define	CSL_DAT_REGION_6  6         /* EDMA Region 6 */
#define	CSL_DAT_REGION_7  7         /* EDMA Region 7 */

#endif  /* _SOC_H_ */