soc.h

Dm6455 driver,magbe useful to you!

/*  ============================================================================
 *  Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
 *
 *  Use of this software is controlled by the terms and conditions found in the
 *  license agreement under which this software has been supplied.
 *  ===========================================================================
 */

#ifndef _SOC_H_
#define _SOC_H_

/* =============================================================================
 *  Revision History
 *  ===============
 *  14-Mar-2005 brn Moved the Event Ids from csl_intc.h to soc64plus.h
 *  20-Jun-2005 sd  Changed the interrupt ID defines
 *  22-Aug-2005 sd  added the defines for MDIO 
 *  14-Dec-2005 sd  updated for the PLLC_2 based address
 * =============================================================================
 */

#include <cslr.h>
/**************************************************************************\
* 64 soc file
\**************************************************************************/

/*****************************************************************************\
* Static inline definition
\*****************************************************************************/
#ifndef CSL_IDEF_INLINE
#define CSL_IDEF_INLINE static inline
#endif

/**************************************************************************\
* Peripheral Instance count
\**************************************************************************/
/** @brief Number of MCBSP instances */
#define CSL_MCBSP_CNT                   2

/** @brief Number of TIMER 64 instances */
#define CSL_TMR_CNT                     2

/** @brief Number of DDR2 instances */
#define CSL_DDR2_CNT                    1

/** @brief Number of EMIF64 instances */
#define CSL_EMIF64_CNT                  1

/** @brief Number of EDMA3 CC instances */
#define CSL_EDMA3_CC_CNT                1

/** @brief Number of EDMA3 CC instances */
#define CSL_EDMA3_TC_CNT                4

/** @brief Number of EMAC instances */
#define CSL_EMAC_CNT                    1

/** @brief Number of ECTL instances */
#define CSL_ECTL_CNT                   1

/** @brief Number of HPI instances */
#define CSL_HPI_CNT                    1

/** @brief Number of UTOPIA instances */
#define CSL_UTOPIA2_CNT                  1

/** @brief Number of I2C instances */
#define CSL_I2C_CNT                     1

/** @brief Number of GPIO instances */
#define CSL_GPIO_CNT                    1

/** @brief Number of VLYNQ instances */
#define CSL_VLYNQ_CNT                   1

/** @brief Number of MDIO instances */
#define CSL_MDIO_CNT                    1

/** @brief Number of SRIO instances */
#define CSL_SRIO_CNT                    1

/**************************************************************************\
* Peripheral Instance definitions.
\**************************************************************************/
/** @brief Peripheral Instances of MCBSP instances */
#define CSL_MCBSP_0                     (0)
#define CSL_MCBSP_1                     (1)

/** @brief Peripheral Instances of Timer 64 instances */
#define CSL_TMR_0                       (0)
#define CSL_TMR_1                       (1)


/** @brief Peripheral Instance of EDMA instances */
#define CSL_EDMA3                       (0)

/** @brief Peripheral Instance for DDR2 */
#define CSL_DDR2                        (0) 

/** @brief Peripheral Instance for EMIFA */
#define  CSL_EMIFA                      (0) 

/** @brief Peripheral Instance for EMAC */
#define  CSL_EMAC                       (0) 

/** @brief Peripheral Instance for ECTL */
#define  CSL_ECTL                      (0) 

/** @brief Peripheral Instance for HPI */
#define CSL_HPI                        (0) 

/** @brief Peripheral Instance for UTOPIA */
#define CSL_UTOPIA2                      (0)

/** @brief Peripheral Instance for I2C */
#define CSL_I2C                         (0) 

/** @brief Peripheral Instance for GPIO */
#define CSL_GPIO				        (0)

/** @brief Peripheral Instance for VLYNQ */
#define CSL_VLYNQ				        (0)

/** @brief Peripheral Instances for MDIO */
#define CSL_MDIO           	            (0) 

/** @brief Peripheral Instances for PWRDWN */
#define CSL_PWRDWN                      (0)

/** @brief Instance number of L2 memory protection */
#define CSL_MEMPROT_L2                  (0) 

/** @brief Instance number of L1P memory protection */
#define CSL_MEMPROT_L1P                 (1) 

/** @brief Instance number of L1D memory protection */
#define CSL_MEMPROT_L1D                 (2) 

/** @brief Instance number of memory protection config */
#define CSL_MEMPROT_CONFIG              (3) 

/** @brief Instance number of Bandwidth Management */
#define CSL_BWMNGMT                     (0) 

/** @brief Instance number of PLL controller 1 */
#define CSL_PLLC_1                     (0) 

/** @brief Instance number of PLL controller 1 */
#define CSL_PLLC_2                     (1) 

/** @brief Instance number of RAPID IO */
#define CSL_SRIO                     (0) 

/** @brief Instance number of device configuration module */
#define CSL_DEV                     (0) 

/**************************************************************************\
* Peripheral Base Address
\**************************************************************************/
/** @brief Base address of MCBSP memory mapped registers */
#define CSL_MCBSP_0_REGS                (0x028C0000u)
#define CSL_MCBSP_1_REGS                (0x02900000u)

/** @brief Base address of MCBSP EDMA memory mapped registers */
#define CSL_MCBSP_0_TX_EDMA_REGS        (0x30000010u)
#define CSL_MCBSP_0_RX_EDMA_REGS        (0x30000000u)
#define CSL_MCBSP_1_TX_EDMA_REGS        (0x34000010u)
#define CSL_MCBSP_1_RX_EDMA_REGS        (0x34000000u)

/** @brief Base address of timer64 memory mapped registers */
#define CSL_TMR_0_REGS                  (0x02940000u)
#define CSL_TMR_1_REGS                  (0x02980000u)

/** #brief DDR2 Module memory mapped address  */
#define CSL_DDR2_0_REGS                 (0x78000000)

/** #brief EMIF64 Module memory mapped address  */
#define CSL_EMIFA_0_REGS                (0x70000000)

/** #brief I2C Module memory mapped address  */
#define CSL_I2C_0_REGS                  (0x02B04000u)

/** #brief Cache Module memory mapped address  */
#define CSL_CACHE_0_REGS                (0x01840000u)

/** #brief IDMA Module memory mapped address  */
#define CSL_IDMA_0_REGS                 (0x01820000u)

/** @brief Base address of INTC memory mapped registers */
#define CSL_INTC_0_REGS                 (0x01800000u)

/** @brief Base address of Channel controller  memory mapped registers */
#define CSL_EDMA3CC_0_REGS              (0x02A00000u)

/** @brief Base address of Transfer controller  memory mapped registers */
#define CSL_EDMA3TC_0_REGS               (0x02A20000u)
#define CSL_EDMA3TC_1_REGS               (0x02A28000u)
#define CSL_EDMA3TC_2_REGS               (0x02A30000u)
#define CSL_EDMA3TC_3_REGS               (0x02A38000u)

/** @brief Base address of TCP2 memory mapped registers */
#define CSL_TCP2_0_REGS                  (0x02BA0000u)

/** @brief Base address of TCP2 configuration registers */
#define CSL_TCP2_CFG_REGS                (0x50000000u) 

/** @brief Base address of TCP2 memories */
#define CSL_TCP2_X0_MEM                 (0x50010000u) 
#define CSL_TCP2_W0_MEM                 (0x50030000u) 
#define CSL_TCP2_W1_MEM                 (0x50040000u) 
#define CSL_TCP2_I0_MEM                 (0x50050000u) 
#define CSL_TCP2_O0_MEM                 (0x50060000u) 
#define CSL_TCP2_S0_MEM                 (0x50070000u) 
#define CSL_TCP2_T0_MEM                 (0x50080000u) 
#define CSL_TCP2_C0_MEM                 (0x50090000u) 
#define CSL_TCP2_A0_MEM                 (0x500A0000u) 
#define CSL_TCP2_B0_MEM                 (0x500B0000u) 

/** @brief Base address of VCP2 memory mapped registers */
#define CSL_VCP2_0_REGS                 (0x02B80000u)

/** @brief Base address of VCP2 regsiters accessed via EDMA */
#define CSL_VCP2_EDMA_REGS              (0x58000000u) 

/** @brief Base address of EMAC memory mapped registers */
#define CSL_EMAC_0_REGS                 (0x02c80000u)

/** @brief Base address of EMAC control memory mapped registers */
#define CSL_ECTL_0_REGS                (0x02C81000u)

/** @brief HPI Module memory mapped address  */
#define CSL_HPI_0_REGS                 (0x02880000u)

/** @brief UTOPIA Module memory mapped address  */
#define CSL_UTOPIA2_0_REGS               (0x02B40000u)

/** @brief UTOPIA RX data Module memory mapped address  */
#define CSL_UTOPIA2_RX_EDMA_REGS          (0x3C000000u)

/** @brief UTOPIA TX data memory mapped address  */
#define CSL_UTOPIA2_TX_EDMA_REGS          (0x3C000400u)

/** @brief GPIO Module memory mapped address  */
#define CSL_GPIO_0_REGS                 (0x02B00000u)

/** @brief VLYNQ Module memory mapped address  */
#define CSL_VLYNQ_0_REGS                (0x38000000u)

/** @brief MDIO Module memory mapped address    */
#define CSL_MDIO_0_REGS                 (0x02C81800u)

/** @brief device configuration registers memory mapped address    */
#define CSL_DEV_REGS                    (0x02A80000u)     

/** @brief Base address of PDC registers */
#define CSL_PWRDWN_PDC_REGS 	        (0x01810000)

/** @brief Base address of L2 power Down registers */
#define CSL_PWRDWN_L2_REGS	            (0x0184c000)

/** @brief Base address of UMC Memory protection registers */
#define CSL_MEMPROT_L2_REGS             (0x184A000u)
 
/** @brief Base address of PMC memory Protection registers */
#define CSL_MEMPROT_L1P_REGS            (0x184A400u)

/** @brief Base address of DMC memory protection registers */
#define CSL_MEMPROT_L1D_REGS            (0x184AC00u)

/** @brief Base address of CONFIG memory protection registers */
#define CSL_MEMPROT_CONFIG_REGS         (0x1820300u)

/** @brief Bandwidth Management module address */
#define CSL_BWMNGMT_0_REGS	            (0x01820200u)

/** @brief PLL controller instance 1 module address */
#define CSL_PLLC_1_REGS	                (0x029A0000u)

/** @brief PLL controller instance 2 module address */
#define CSL_PLLC_2_REGS	                (0x029C0000u)

/** @brief EDC module base address */
#define CSL_EDC_0_REGS		            (0x01846000u)

/** @brief SRIO module base address */
#define CSL_SRIO_0_REGS                 (0x02D00000u)


/******************************************************************************\
* EMAC Descriptor section
\******************************************************************************/

#define CSL_EMAC_DSC_BASE_ADDR         0x02c82000u
#define CSL_EMAC_DSC_BASE_ADDR_L2      0x00900800u

/* EMAC Descriptor Size and Element Count */
#define CSL_EMAC_DSC_SIZE              8192
#define CSL_EMAC_DSC_ENTRY_SIZE        16	/* Size of a buffer descriptor, in bytes */
#define CSL_EDMA_DSC_ENTRY_COUNT       (CSL_EMAC_DSC_SIZE/CSL_EMAC_DSC_ENTRY_SIZE)	/* 512 */


/*****************************************************************************\
* Interrupt Event IDs
\*****************************************************************************/

/**
 * @brief   Interrupt Event IDs
 */
/* Output of event combiner 0, for events 1 to 31  */
#define    CSL_INTC_EVENTID_EVT0            (0)              
/* Output of event combiner 0, for events 32 to 63 */
#define    CSL_INTC_EVENTID_EVT1            (1)              
/* Output of event combiner 0, for events 64 to 95 */
#define    CSL_INTC_EVENTID_EVT2            (2)              
/* Output of event combiner 0, for events 96 to 127 */
#define    CSL_INTC_EVENTID_EVT3            (3)              

/* Event ID 4-8 are reserved */

/** EMU interrupt for: 
  * 1. Host scan access 
  * 2. DTDMA transfer complete
  * 3. AET interrupt
  */    
#define    CSL_INTC_EVENTID_EMU_DTDMA       (9)         

/* Event ID 10 is reserved */

/* EMU real time data exchange receive complete    */
#define    CSL_INTC_EVENTID_EMU_RTDXRX      (11)        
/* EMU RTDX transmit complete   */
#define    CSL_INTC_EVENTID_EMU_RTDXTX      (12)        
/* IDMA Channel 0 Interrupt */
#define    CSL_INTC_EVENTID_IDMA0           (13)        
/* IDMA Channel 1 Interrupt */
#define    CSL_INTC_EVENTID_IDMA1           (14)        
/* HPI/PCI Host interrupt   */
#define    CSL_INTC_EVENTID_HINT            (15)        
/* I2C interrupt            */
#define    CSL_INTC_EVENTID_I2CINT          (16)        
/* Ethernet MAC interrupt   */
#define    CSL_INTC_EVENTID_MACINT          (17)        
/* EMIFA Error Interrupt    */
#define    CSL_INTC_EVENTID_AEASYNCERR      (18)   
     
/* Event ID 19 is reserved  */

/* RapidIO interrupt 0      */
#define    CSL_INTC_EVENTID_RIOINT0         (20)        
/* RapidIO interrupt 1      */
#define    CSL_INTC_EVENTID_RIOINT1         (21)        
/* RapidIO interrupt 4            */
#define    CSL_INTC_EVENTID_RIOINT4         (22)        

/* Event ID 23 is reserved */

/* EDMA3 channel global completion interrupt */
#define    CSL_INTC_EVENTID_EDMA3CC_GINT         (24)        

/* Event ID 25-29 is reserved */    

/* L2 Wakeup interrupt 0      */
#define    CSL_INTC_EVENTID_L2PDWAKE0       (30)        
/* L2 Wakeup interrupt 1      */
#define    CSL_INTC_EVENTID_L2PDWAKE1       (31)        
/* VCP2 error interrupt     */
#define    CSL_INTC_EVENTID_VCP2_INT        (32)        
/* TCP2 error interrupt     */
#define    CSL_INTC_EVENTID_TCP2_INT        (33)        

/* Event ID 34-35 is reserved */ 

/* Utopia interrupt         */
#define    CSL_INTC_EVENTID_UINT            (36)        

/* Event ID 37-39 is reserved */ 

/* McBSP0 receive interrupt */