syslib.c

VxWOrks中bspMCF5200下的Nand Flash TFFS的驱动程序。

/* sysLib.c - Motorola m5272c3 system-dependent library */

/* Copyright 1984-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01e,02may03,dee  fix SPR 87763
01d,25mar02,rec  fix endian problem with enet address
01c,01mar02,rec  Add NVRAM support (spr 74038)
01b,30jan02,dee  cleanup warnings for Diab compiler
01a,20mar01,hjg  Written based on m5206ec3 BSP.
*/

/*
DESCRIPTION
This library provides board-specific routines for the Motorola m5272c3
development system.

INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "errno.h"
#include "stdarg.h"
#include "cacheLib.h"
#include "memLib.h"
#include "vxLib.h"
#include "sysLib.h"
#include "ioLib.h"
#include "config.h"
#include "intLib.h"
/*#include "drv/multi/m5272.h"*/
#include "arch/coldfire/vxColdfireLib.h"
#include "string.h"


#include "coldfireTimer.h"


/* globals */

char sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */
int  sysFlags;				/* boot flags			*/
int  sysCpu	    = CPU;		/* system cpu type		   */
char *sysBootLine   = BOOT_LINE_ADRS;	/* address of boot line	      */
char *sysExcMsg	    = EXC_MSG_ADRS;	/* catastrophic message area	 */

/*  externals */

extern	void sysClearCache(void);
extern     void mcf5xxx_wr_cacr(int );

#ifdef INCLUDE_END
unsigned char motFecEnetAddr[] = { 0x00, 0xcf, 0x52, 0x72, 0xc3, 0x01 };
INT16 motFecPhyAnOrderTbl [] = {-1};	/* Not used */
#endif

#ifdef INCLUDE_CACHE_SUPPORT
 #include "cacheMCF5204Lib.c"
ULONG initialCACR = 0x00000400; /* enable burst fetchs */
IMPORT  STATUS  cacheMCF5204LibInit ();
FUNCPTR sysCacheLibInit = (FUNCPTR) cacheMCF5204LibInit;

#else /* INCLUDE_CACHE_SUPPORT */

FUNCPTR sysCacheLibInit = NULL;

#endif /* INCLUDE_CACHE_SUPPORT */

/* locals */
int	sysProcNum;		/* processor number of this cpu      */

/* forward declarations */
LOCAL	void	sysChipSelectInit (void);
LOCAL	void	sysSimInit (void);
LOCAL	void	sysIntInit (void);
LOCAL	void	sysBusInit (void);
LOCAL	void	sysDmaInit (void);
LOCAL	void	sysTimerInit (void);

#include "sysSerial.c"
#include "motFecEnd.c"

#ifdef ETHERNET_ADR_SET
STATUS sysEnetAddrGet(int unit, UINT8 *	addr);
#endif /* ETHERNET_ADR_SET */

#include "coldfireTimer.c"
#if defined(AMD_FLASH_AM29PL160CB_16BIT)
#  include "mem/flashMem.c"
#  include "mem/nvRamToFlash.c"
#else
#  include "mem/nullNvRam.c"
#endif  /* INCLUDE_NV_RAM || INCLUDE_FLASH */
/*#include "am29lvxxx.c"*/


/******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* RETURNS: A pointer to the string "Motorola M5272C3".
*/

char *sysModel (void)
    {
    return ("Motorola M5235");
    }


/*******************************************************************************
*
* sysBspRev - return the bsp version with the revision eg 1.1/<x>
*
* This function returns a pointer to a bsp version with the revision.
* for eg. 1.1/<x>. BSP_REV is concatanated to BSP_VERSION to form the
* BSP identification string.
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char *sysBspRev (void)
    {
    return (BSP_VERSION BSP_REV);
    }


/******************************************************************************
*
* sysHwInit - initialize the CPU board hardware
*
* This routine initializes various features of the M5272C3.
* It is called from usrInit() in usrConfig.c.
*
* NOTE: This routine should not be called directly by the user.
*
* RETURNS: N/A
*/

void sysHwInit (void)
    {
#if 0
     mcf5xxx_wr_cacr(0| MCF5XXX_CACR_CENB|MCF5XXX_CACR_CPDI|MCF5XXX_CACR_CEIB| MCF5XXX_CACR_CLNF_00); /* | MCF5XXX_CACR_DISD | MCF5XXX_CACR_CEIB MCF5XXX_CACR_CPDI*/
#endif

    /* initialize all of the various subsystems */
    sysSimInit ();
    sysChipSelectInit ();
    sysIntInit ();
    sysBusInit ();
   /* sysDmaInit ();*/
    sysTimerInit ();

    /* initialize the serial devices */
    sysSerialHwInit ();

  
    /* initialise MAC support */
#ifdef INCLUDE_MAC_SUPPORT
    vxMacSupport(TRUE);
#endif

    }


/******************************************************************************
*
* sysHwInit2 - additional system configuration and initialization
*
* This routine connects system interrupts and does any additional
* configuration necessary.
*
* RETURNS: N/A
*
* NOMANUAL
*/

void sysHwInit2 (void)
    {


#if defined(INCLUDE_COLDFIRE_SYS_CLK)
    intConnect (INUM_TO_IVEC(MCF_INTC0_LVL_TMR0), sysClkInt, 0);
#endif
#if defined(INCLUDE_COLDFIRE_AUX_CLK)
    intConnect (INUM_TO_IVEC(MCF_INTC0_LVL_TMR1), sysAuxClkInt, 0);
#endif

    /* connect serial interrupts */
    sysSerialHwInit2 ();


    /* 
     * Allow interrupts from IRQ7 (black button) 
     */
    /* *MCF_EPORT_EPIER = MCF_EPORT_EPIER_EPIE7;*/ /*jason*/
/**
  * USB int initialize EDGE PORT MODULE
  *
  * jason start*/
 *MCF_EPORT_EPPAR = MCF_EPORT_EPPAR_EPPA3(MCF_EPORT_EPPAR_EPPAx_RISING)|MCF_EPORT_EPPAR_EPPA7(MCF_EPORT_EPPAR_EPPAx_RISING);
 *MCF_EPORT_EPDDR = 0;
 *MCF_EPORT_EPIER =  MCF_EPORT_EPIER_EPIE3  |  MCF_EPORT_EPIER_EPIE7;
  /**MCF_EPORT_EPDR =
 *MCF_EPORT_EPPDR =
 *MCF_EPORT_EPFR = */
/*jason end*/
/**MCF_EPORT_EPIER |= MCF_EPORT_EPIER_EPIE7;*/ /*jason*/
    *MCF_INTC0_IMRL &=   ~(MCF_INTC0_INTFRCL_INT7 | MCF_INTC0_IMRL_MASKALL);
    //in order to initial the MCF_INTC1_IMRL ,now the 0bit is 0,
    *MCF_INTC1_IMRL &=   ~MCF_INTC0_IMRL_MASKALL;

/*2007-5-16 11:20 以太网*/
*sysBootLine = EOS;//清除sysBootLine（BOOT_LINE_ADRS）
/*2007-5-16 11:20 以太网*/


    }


/******************************************************************************
*
* sysSimInit - initialize the SIM (system integration module).
*
* RETURNS: N/A
*
* NOMANUAL
*/

LOCAL void sysSimInit (void)
    {
#if 0
    /* Set hardware watchdog time. */
    *M5272_SIM_SCR(SIM_BASE) = M5272_SIM_SCR_HWR_1024;

    /* Enable clocks to all modules */
    *M5272_SIM_PMR(SIM_BASE) = 0;

    /* Enable all bus error exceptions */
    *M5272_SIM_SPR(SIM_BASE) = M5272_SIM_SPR_ADCEN |
			       M5272_SIM_SPR_WPVEN |
			       M5272_SIM_SPR_SMVEN |
			       M5272_SIM_SPR_PEVEN |
			       M5272_SIM_SPR_HWTEN |
			       M5272_SIM_SPR_RPVEN |
			       M5272_SIM_SPR_EXTEN |
			       M5272_SIM_SPR_SUVEN;

    /* Disable all interrupts */
    *M5272_SIM_ICR1(SIM_BASE) = 0x88888888;
    *M5272_SIM_ICR2(SIM_BASE) = 0x88888888;
    *M5272_SIM_ICR3(SIM_BASE) = 0x88888888;
    *M5272_SIM_ICR4(SIM_BASE) = 0x88888888;

    /* All external interrupts trigger on falling edge */
    *M5272_SIM_PITR(SIM_BASE) = M5272_SIM_PITR_NEG_EDGE;

    /* No wakeup for any interrupt */
    *M5272_SIM_PIWR(SIM_BASE) = 0xfffffff0;

    /* Peripheral interrupt vectors begin at defined base */
    *M5272_SIM_PIVR(SIM_BASE) = INT_NUM_BASE;

    /* Watchdogs: disable & clear. */
    *M5272_SIM_WRRR(SIM_BASE) = M5272_SIM_WRRR_REF;	/* max time, disable */
    *M5272_SIM_WIRR(SIM_BASE) = M5272_SIM_WIRR_REF;	/* max time, disable */
    *M5272_SIM_WCR(SIM_BASE) = 0;			/* reset counter */
    *M5272_SIM_WER(SIM_BASE) = M5272_SIM_WER_WIE;	/* clear event */
#endif
    /* Stop all timers */
    *MCF_TIMER_DTMR(0) = 0x00;
    *MCF_TIMER_DTMR(1) = 0x00;
    *MCF_TIMER_DTMR(2) = 0x00;
    *MCF_TIMER_DTMR(3) = 0x00;
    }


/******************************************************************************
*
* sysChipSelectInit - initialize the chip selects.
*
* The important chip selects are CS0 (flash) and CS3 (ethernet).
* The rest aren't used in the default configuration, although
* CS2 runs to the external SRAM when it's fitted.
*
* RETURNS: N/A
*
* NOMANUAL
*/

LOCAL void sysChipSelectInit (void)
    {

	#if 0
       /* 
     * ChipSelect 0 - External Flash 
     */
#ifdef AMD_FLASH_AM29PL160CB_16BIT
    MCF_CS_CSAR0 = MCF_CS_CSAR_BA(FLASH_ADDRESS);
    MCF_CS_CSCR0 = (0
        | MCF_CS_CSCR_IWS((int)(AMD_FLASH_SPEED/SYSTEM_CLK_PERIOD))
        | MCF_CS_CSCR_AA
        | MCF_CS_CSCR_PS_16);
    MCF_CS_CSMR0 = MCF_CS_CSMR_BAM_2M | MCF_CS_CSMR_V;
#else   
    MCF_CS_CSAR0 = MCF_CS_CSAR_BA(FLASH_ADDRESS);
    MCF_CS_CSCR0 = (0
        | MCF_CS_CSCR_IWS((int)(AMD_FLASH_SPEED/SYSTEM_CLK_PERIOD))
        | MCF_CS_CSCR_AA
        | MCF_CS_CSCR_PS_32);
    MCF_CS_CSMR0 = MCF_CS_CSMR_BAM_4M | MCF_CS_CSMR_V;
#endif  
#endif
/*2007-4-9 11:32 mengjun end if 1*/
#if 1
/**
  * isp1362 selected
  *
  * jason start*/
    *MCF_CS_CSAR1 = 0x3200;
    *MCF_CS_CSCR1 = 0xfd47 ;
    *MCF_CS_CSMR1 = MCF_CS_CSMR_BAM_1M | MCF_CS_CSMR_V;
    //*MCF_CS_CSMR1 = 0x00070001 ;
/*jason end*/

/**
  * isp1362 selected
  *
  * jason start*/
    *MCF_CS_CSAR2 =0x3000; /*MCF_CS_CSAR_BA(ISP1362_BA);*/
    *MCF_CS_CSCR2 = (0
        | MCF_CS_CSCR_IWS((int)(ISP1362_SPEED/SYSTEM_CLK_PERIOD))
        | MCF_CS_CSCR_AA
        | MCF_CS_CSCR_PS_16);
    *MCF_CS_CSMR2 = MCF_CS_CSMR_BAM_64K | MCF_CS_CSMR_V;
/*jason end*/


#endif/*#if 1*/

/*2007-4-9 11:32 mengjun */
    }


/******************************************************************************
*
* sysIntInit - initialize the interrupt subsystem
*
* RETURNS: N/A
*
* NOMANUAL
*/

LOCAL void sysIntInit (void)
    {


   /* mask all interrupt sources */
   *MCF_INTC0_IMRL = MCF_INTC0_IMRL_MASKALL;
    *MCF_INTC1_IMRL = MCF_INTC1_IMRL_MASKALL;


    /* initialize Interrupt Control Registers */

	 /* Set SCM Interrupt Control Register */
	 *MCF_INTC0_ICRn(8) = MCF_INTC0_ICRn_IL(7) | MCF_INTC0_ICRn_IP(2);
	   /* Set DMA Interrupt Control Register */
	 *MCF_INTC0_ICRn(9) = MCF_INTC0_ICRn_IL(2) | MCF_INTC0_ICRn_IP(0);
 	 *MCF_INTC0_ICRn(10) = MCF_INTC0_ICRn_IL(2) | MCF_INTC0_ICRn_IP(1);
	 *MCF_INTC0_ICRn(11) = MCF_INTC0_ICRn_IL(2) | MCF_INTC0_ICRn_IP(2);
        *MCF_INTC0_ICRn(12) = MCF_INTC0_ICRn_IL(2) | MCF_INTC0_ICRn_IP(3);
	
	           /* Set UART  Interrupt Control Register */
	  *MCF_INTC0_ICRn(13) = MCF_INTC0_ICRn_IL(4) | MCF_INTC0_ICRn_IP(2);  
	  *MCF_INTC0_ICRn(14) = MCF_INTC0_ICRn_IL(5) | MCF_INTC0_ICRn_IP(1);
	  *MCF_INTC0_ICRn(15) = MCF_INTC0_ICRn_IL(5) | MCF_INTC0_ICRn_IP(0);
	
	  
         /* Set Timer Interrupt Control Register */
	  *MCF_INTC0_ICRn(19) = MCF_INTC0_ICRn_IL(6) | MCF_INTC0_ICRn_IP(3);
	  *MCF_INTC0_ICRn(20) = MCF_INTC0_ICRn_IL(6) | MCF_INTC0_ICRn_IP(1);
	  
        /* FEC Rx Frame */
        *MCF_INTC0_ICRn(27) = MCF_INTC0_ICRn_IL(4) | MCF_INTC0_ICRn_IP(7);
        /* FEC Rx Buffer */                              
        *MCF_INTC0_ICRn(28) = MCF_INTC0_ICRn_IL(4) | MCF_INTC0_ICRn_IP(6);
        /* FEC Tx Frame */                               
        *MCF_INTC0_ICRn(23) = MCF_INTC0_ICRn_IL(4) | MCF_INTC0_ICRn_IP(5);
        /* FEC Tx Buffer */                              
        *MCF_INTC0_ICRn(24) = MCF_INTC0_ICRn_IL(4) | MCF_INTC0_ICRn_IP(4);
        /* FEC FIFO Underrun */                              
        *MCF_INTC0_ICRn(25) = MCF_INTC0_ICRn_IL(4) | MCF_INTC0_ICRn_IP(3);
        /* FEC Collision Retry Limit */                              
        *MCF_INTC0_ICRn(26) = MCF_INTC0_ICRn_IL(4) |MCF_INTC0_ICRn_IP(2);
        /* FEC MII */                                
        *MCF_INTC0_ICRn(29) = MCF_INTC0_ICRn_IL(4) |MCF_INTC0_ICRn_IP(1);
        /* FEC Late Collision */                                 
        *MCF_INTC0_ICRn(30) = MCF_INTC0_ICRn_IL(4) |MCF_INTC0_ICRn_IP(0);
        /* FEC Heartbeat Error */                                
        *MCF_INTC0_ICRn(31) = MCF_INTC0_ICRn_IL(3) |MCF_INTC0_ICRn_IP(7);
        /* FEC Graceful Stop Comlete */                              
        *MCF_INTC0_ICRn(32) = MCF_INTC0_ICRn_IL(3) |MCF_INTC0_ICRn_IP(6);
        /* FEC Bus Error */                              
        *MCF_INTC0_ICRn(33) = MCF_INTC0_ICRn_IL(3) |MCF_INTC0_ICRn_IP(5);
        /* FEC Babbling Transmit */                              
        *MCF_INTC0_ICRn(34) = MCF_INTC0_ICRn_IL(3) | MCF_INTC0_ICRn_IP(4);
        /* FEC Babbling Receive */                               
        *MCF_INTC0_ICRn(35) = MCF_INTC0_ICRn_IL(3) | MCF_INTC0_ICRn_IP(3);

/**
  * USB int initialize to intNO = 67
  *
  * jason start*/
       *MCF_INTC0_ICRn(3) = MCF_INTC0_ICRn_IL(3) | MCF_INTC0_ICRn_IP(2);/*??jason??*/
/*jason end*/

#if 0
								 
        /* Enable the FEC interrupts in the mask register */    
        *MCF_INTC0_IMRL &= ~(MCF_INTC0_IMRL_INT_MASK23 |
                            MCF_INTC0_IMRL_INT_MASK24 |
                            MCF_INTC0_IMRL_INT_MASK25 |
                            MCF_INTC0_IMRL_INT_MASK26 |
                            MCF_INTC0_IMRL_INT_MASK27 |
                            MCF_INTC0_IMRL_INT_MASK28 |
                            MCF_INTC0_IMRL_INT_MASK29 |
                            MCF_INTC0_IMRL_INT_MASK30 |
                            MCF_INTC0_IMRL_INT_MASK31 |
                            MCF_INTC0_IMRL_MASKALL);
        *MCF_INTC0_IMRH &= ~(MCF_INTC0_IMRH_INT_MASK32 |
                            MCF_INTC0_IMRH_INT_MASK33 |
                            MCF_INTC0_IMRH_INT_MASK34 |
                            MCF_INTC0_IMRH_INT_MASK35);
#endif
    }


/******************************************************************************
*
* sysBusInit - initialize the bus subsystem
*
* RETURNS: N/A
*
* NOMANUAL
*/

LOCAL void sysBusInit (void)
    {

      /*Initialize PAR to enable DMATimer 0-3  */
      *MCF_GPIO_PAR_TIMER = 0xFFFF;

      /* Initialize PAR to enable Ethernet and CAN0 signals  */
     *MCF_GPIO_PAR_FECI2C = 0xFA;
     *MCF_GPIO_PDDR_FECI2C = 0x0F;
	 
  /* 
     * Set Port UA to initialize URXD0/URXD1 UTXD0/UTXD1 
                                     CAN1
     */
    *MCF_GPIO_PAR_UART = 0x40FF;

    }


/******************************************************************************
*
* sysDmaInit - initialize the dma subsystem
*
* RETURNS: N/A