📄 test_con.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity test_con is
end test_con;
architecture behave of test_con is
component t_control
port(t_low,t_high : in std_logic;
Rd,clk : in std_logic;
ch : out std_logic_vector(1 downto 0));
end component;
signal t_low,t_high : std_logic;
signal Rd,clk : std_logic;
signal ch : std_logic_vector(1 downto 0);
begin
u1 : t_control port map (t_low,t_high,Rd,clk,ch);
t_low <= '0' ,'1' after 50 ns,'0' after 100ns,
'1' after 150 ns,'0' after 200ns,
'1' after 250 ns,'0' after 300ns,
'1' after 350 ns,'0' after 400ns,
'1' after 450 ns,'0' after 500ns,
'1' after 550 ns,'0' after 600ns;
t_high <= '0' ,'1' after 100 ns,'0' after 150ns,
'1' after 200 ns,'0' after 250ns,
'1' after 300 ns,'0' after 350ns,
'1' after 450 ns,'0' after 500ns,
'1' after 550 ns,'0' after 600ns,
'1' after 650 ns,'0' after 700ns,
'1' after 750 ns,'0' after 800ns;
Rd <= '0','1' after 20 ns;
clk <= '0','1' after 50 ns,'0' after 100ns,
'1' after 150 ns,'0' after 200ns,
'1' after 250 ns,'0' after 300ns,
'1' after 350 ns,'0' after 400ns,
'1' after 450 ns,'0' after 500ns,
'1' after 550 ns,'0' after 600ns;
end behave;
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