📄 t_control.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity t_control is
port(t_low,t_high : in std_logic;
Rd,clk : in std_logic;
ch : out std_logic_vector(1 downto 0));
end t_control;
architecture behave of t_control is
type s_m is (s0,s1,s2);
signal cur_state : s_m;
signal next_state : s_m;
signal tt : std_logic_vector(1 downto 0);
begin
tt <= t_low & t_high;
func1 : process(tt,cur_state)
begin
case cur_state is
when s0 => if tt = "00" then next_state <= s0;
elsif tt = "01" then next_state <= s1;
else next_state <= s2;
end if;
when s1 => if tt = "00" then next_state <= s0;
elsif tt = "01" then next_state <= s1;
else next_state <= s2;
end if;
when s2 => if tt = "00" then next_state <= s0;
elsif tt = "01" then next_state <= s1;
else next_state <= s2;
end if ;
end case;
end process;
reg : process(clk,Rd)
begin
if Rd = '0' then cur_state <= s0;
elsif clk'event and clk = '1' then cur_state <= next_state;
end if ;
end process;
func2 : process(cur_state)
begin
case cur_state is
when s0 => ch <= "00";
when s1 => ch <= "10";
when s2 => ch <= "01";
end case;
end process;
end behave;
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