i2c.map.qmsg

i2c总线的CPLD程序

{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|i2c\|i2c_state 5 " "Info: State machine \"\|i2c\|i2c_state\" contains 5 states" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 35 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|i2c\|inner_state 11 " "Info: State machine \"\|i2c\|inner_state\" contains 11 states" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|i2c\|main_state " "Info: Selected Auto state machine encoding method for state machine \"\|i2c\|main_state\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 34 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|i2c\|main_state " "Info: Encoding result for state machine \"\|i2c\|main_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main_state.00 " "Info: Encoded state bit \"main_state.00\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 34 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main_state.10 " "Info: Encoded state bit \"main_state.10\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 34 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main_state.01 " "Info: Encoded state bit \"main_state.01\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 34 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|main_state.00 000 " "Info: State \"\|i2c\|main_state.00\" uses code string \"000\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 34 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|main_state.01 101 " "Info: State \"\|i2c\|main_state.01\" uses code string \"101\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 34 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|main_state.10 110 " "Info: State \"\|i2c\|main_state.10\" uses code string \"110\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 34 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 34 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|i2c\|i2c_state " "Info: Selected Auto state machine encoding method for state machine \"\|i2c\|i2c_state\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 35 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|i2c\|i2c_state " "Info: Encoding result for state machine \"\|i2c\|i2c_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_state.read_data " "Info: Encoded state bit \"i2c_state.read_data\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 35 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_state.sendaddr " "Info: Encoded state bit \"i2c_state.sendaddr\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 35 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_state.write_data " "Info: Encoded state bit \"i2c_state.write_data\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 35 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_state.ini " "Info: Encoded state bit \"i2c_state.ini\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 35 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_state.read_ini " "Info: Encoded state bit \"i2c_state.read_ini\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 35 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_state.ini 00000 " "Info: State \"\|i2c\|i2c_state.ini\" uses code string \"00000\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 35 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_state.read_ini 00011 " "Info: State \"\|i2c\|i2c_state.read_ini\" uses code string \"00011\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 35 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_state.write_data 00110 " "Info: State \"\|i2c\|i2c_state.write_data\" uses code string \"00110\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 35 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_state.sendaddr 01010 " "Info: State \"\|i2c\|i2c_state.sendaddr\" uses code string \"01010\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 35 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|i2c_state.read_data 10010 " "Info: State \"\|i2c\|i2c_state.read_data\" uses code string \"10010\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 35 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 35 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|i2c\|inner_state " "Info: Selected Auto state machine encoding method for state machine \"\|i2c\|inner_state\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|i2c\|inner_state " "Info: Encoding result for state machine \"\|i2c\|inner_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "11 " "Info: Completed encoding using 11 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "inner_state.stop " "Info: Encoded state bit \"inner_state.stop\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "inner_state.first " "Info: Encoded state bit \"inner_state.first\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "inner_state.second " "Info: Encoded state bit \"inner_state.second\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "inner_state.third " "Info: Encoded state bit \"inner_state.third\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "inner_state.fourth " "Info: Encoded state bit \"inner_state.fourth\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "inner_state.fifth " "Info: Encoded state bit \"inner_state.fifth\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "inner_state.sixth " "Info: Encoded state bit \"inner_state.sixth\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "inner_state.seventh " "Info: Encoded state bit \"inner_state.seventh\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "inner_state.eighth " "Info: Encoded state bit \"inner_state.eighth\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "inner_state.ack " "Info: Encoded state bit \"inner_state.ack\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "inner_state.start " "Info: Encoded state bit \"inner_state.start\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|inner_state.start 00000000000 " "Info: State \"\|i2c\|inner_state.start\" uses code string \"00000000000\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|inner_state.ack 00000000011 " "Info: State \"\|i2c\|inner_state.ack\" uses code string \"00000000011\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|inner_state.eighth 00000000101 " "Info: State \"\|i2c\|inner_state.eighth\" uses code string \"00000000101\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|inner_state.seventh 00000001001 " "Info: State \"\|i2c\|inner_state.seventh\" uses code string \"00000001001\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|inner_state.sixth 00000010001 " "Info: State \"\|i2c\|inner_state.sixth\" uses code string \"00000010001\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|inner_state.fifth 00000100001 " "Info: State \"\|i2c\|inner_state.fifth\" uses code string \"00000100001\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|inner_state.fourth 00001000001 " "Info: State \"\|i2c\|inner_state.fourth\" uses code string \"00001000001\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|inner_state.third 00010000001 " "Info: State \"\|i2c\|inner_state.third\" uses code string \"00010000001\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|inner_state.second 00100000001 " "Info: State \"\|i2c\|inner_state.second\" uses code string \"00100000001\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|inner_state.first 01000000001 " "Info: State \"\|i2c\|inner_state.first\" uses code string \"01000000001\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c\|inner_state.stop 10000000001 " "Info: State \"\|i2c\|inner_state.stop\" uses code string \"10000000001\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "clk_div\[0\] cnt_scan\[0\] " "Info: Duplicate register \"clk_div\[0\]\" merged to single register \"cnt_scan\[0\]\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 109 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "clk_div\[1\] cnt_scan\[1\] " "Info: Duplicate register \"clk_div\[1\]\" merged to single register \"cnt_scan\[1\]\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 109 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "lowbit GND " "Warning: Pin \"lowbit\" stuck at GND" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 18 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "seg_data\[0\] VCC " "Warning: Pin \"seg_data\[0\]\" stuck at VCC" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 20 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 13 -1 0 } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 706 -1 0 } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 692 -1 0 } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 692 -1 0 } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 29 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "6 6 " "Info: 6 registers lost all their fanouts during netlist optimizations. The first 6 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "i2c_state~65 " "Info: Register \"i2c_state~65\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "i2c_state~66 " "Info: Register \"i2c_state~66\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "inner_state~140 " "Info: Register \"inner_state~140\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "inner_state~141 " "Info: Register \"inner_state~141\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "inner_state~142 " "Info: Register \"inner_state~142\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "inner_state~143 " "Info: Register \"inner_state~143\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "296 " "Info: Implemented 296 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "8 " "Info: Implemented 8 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "1 " "Info: Implemented 1 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "275 " "Info: Implemented 275 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "125 " "Info: Allocated 125 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jul 06 20:50:47 2008 " "Info: Processing ended: Sun Jul 06 20:50:47 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}