i2c.map.qmsg

i2c总线的CPLD程序

{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "addr i2c.v(114) " "Warning (10240): Verilog HDL Always Construct warning at i2c.v(114): inferring latch(es) for variable \"addr\", which holds its previous value in one or more paths through the always construct" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 114 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr\[7\] i2c.v(40) " "Info (10041): Verilog HDL or VHDL info at i2c.v(40): inferred latch for \"addr\[7\]\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr\[6\] i2c.v(40) " "Info (10041): Verilog HDL or VHDL info at i2c.v(40): inferred latch for \"addr\[6\]\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr\[5\] i2c.v(40) " "Info (10041): Verilog HDL or VHDL info at i2c.v(40): inferred latch for \"addr\[5\]\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr\[4\] i2c.v(40) " "Info (10041): Verilog HDL or VHDL info at i2c.v(40): inferred latch for \"addr\[4\]\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr\[3\] i2c.v(40) " "Info (10041): Verilog HDL or VHDL info at i2c.v(40): inferred latch for \"addr\[3\]\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr\[2\] i2c.v(40) " "Info (10041): Verilog HDL or VHDL info at i2c.v(40): inferred latch for \"addr\[2\]\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr\[1\] i2c.v(40) " "Info (10041): Verilog HDL or VHDL info at i2c.v(40): inferred latch for \"addr\[1\]\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "addr\[0\] i2c.v(40) " "Info (10041): Verilog HDL or VHDL info at i2c.v(40): inferred latch for \"addr\[0\]\"" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 i2c.v(703) " "Warning (10230): Verilog HDL assignment warning at i2c.v(703): truncated value with size 32 to match size of target (12)" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 703 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(711) " "Info (10264): Verilog HDL Case Statement information at i2c.v(711): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 711 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "writeData_reg\[7\] data_in GND " "Warning: Reduced register \"writeData_reg\[7\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 692 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "writeData_reg\[6\] data_in GND " "Warning: Reduced register \"writeData_reg\[6\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 692 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "writeData_reg\[5\] data_in GND " "Warning: Reduced register \"writeData_reg\[5\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 692 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "writeData_reg\[4\] data_in GND " "Warning: Reduced register \"writeData_reg\[4\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 692 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|i2c\|main_state 3 " "Info: State machine \"\|i2c\|main_state\" contains 3 states" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 34 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}