i2c.map.qmsg

i2c总线的CPLD程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jul 06 20:50:43 2008 " "Info: Processing started: Sun Jul 06 20:50:43 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off i2c -c i2c " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off i2c -c i2c" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file i2c.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c " "Info: Found entity 1: i2c" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "i2c " "Info: Elaborating entity \"i2c\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 i2c.v(72) " "Warning (10230): Verilog HDL assignment warning at i2c.v(72): truncated value with size 32 to match size of target (20)" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 72 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 i2c.v(90) " "Warning (10230): Verilog HDL assignment warning at i2c.v(90): truncated value with size 32 to match size of target (8)" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 90 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(155) " "Info (10264): Verilog HDL Case Statement information at i2c.v(155): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 155 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(231) " "Info (10264): Verilog HDL Case Statement information at i2c.v(231): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 231 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(296) " "Info (10264): Verilog HDL Case Statement information at i2c.v(296): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 296 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(153) " "Info (10264): Verilog HDL Case Statement information at i2c.v(153): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 153 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(377) " "Info (10264): Verilog HDL Case Statement information at i2c.v(377): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 377 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(453) " "Info (10264): Verilog HDL Case Statement information at i2c.v(453): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 453 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(518) " "Info (10264): Verilog HDL Case Statement information at i2c.v(518): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 518 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(593) " "Info (10264): Verilog HDL Case Statement information at i2c.v(593): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 593 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(375) " "Info (10264): Verilog HDL Case Statement information at i2c.v(375): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 375 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}