i2c.tan.qmsg

i2c总线的CPLD程序

{ "Info" "ITDB_TSU_RESULT" "sda_buf sda clk 7.489 ns register " "Info: tsu for register \"sda_buf\" (data pin = \"sda\", clock pin = \"clk\") is 7.489 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.513 ns + Longest pin register " "Info: + Longest pin to register delay is 14.513 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sda 1 PIN PIN_78 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_78; Fanout = 1; PIN Node = 'sda'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { sda } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns sda~1 2 COMB IOC_X17_Y3_N2 4 " "Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X17_Y3_N2; Fanout = 4; COMB Node = 'sda~1'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.132 ns" { sda sda~1 } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.612 ns) + CELL(0.914 ns) 7.658 ns Selector67~491 3 COMB LC_X13_Y7_N4 3 " "Info: 3: + IC(5.612 ns) + CELL(0.914 ns) = 7.658 ns; Loc. = LC_X13_Y7_N4; Fanout = 3; COMB Node = 'Selector67~491'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.526 ns" { sda~1 Selector67~491 } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 518 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.788 ns) + CELL(0.511 ns) 8.957 ns Selector27~462 4 COMB LC_X13_Y7_N0 1 " "Info: 4: + IC(0.788 ns) + CELL(0.511 ns) = 8.957 ns; Loc. = LC_X13_Y7_N0; Fanout = 1; COMB Node = 'Selector27~462'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.299 ns" { Selector67~491 Selector27~462 } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 296 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.765 ns) + CELL(0.511 ns) 10.233 ns Selector27~464 5 COMB LC_X13_Y7_N1 1 " "Info: 5: + IC(0.765 ns) + CELL(0.511 ns) = 10.233 ns; Loc. = LC_X13_Y7_N1; Fanout = 1; COMB Node = 'Selector27~464'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.276 ns" { Selector27~462 Selector27~464 } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 296 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.872 ns) + CELL(0.511 ns) 12.616 ns Selector110~650 6 COMB LC_X12_Y8_N8 1 " "Info: 6: + IC(1.872 ns) + CELL(0.511 ns) = 12.616 ns; Loc. = LC_X12_Y8_N8; Fanout = 1; COMB Node = 'Selector110~650'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.383 ns" { Selector27~464 Selector110~650 } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.714 ns) + CELL(1.183 ns) 14.513 ns sda_buf 7 REG LC_X12_Y8_N0 20 " "Info: 7: + IC(0.714 ns) + CELL(1.183 ns) = 14.513 ns; Loc. = LC_X12_Y8_N0; Fanout = 20; REG Node = 'sda_buf'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.897 ns" { Selector110~650 sda_buf } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.762 ns ( 32.81 % ) " "Info: Total cell delay = 4.762 ns ( 32.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.751 ns ( 67.19 % ) " "Info: Total interconnect delay = 9.751 ns ( 67.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "14.513 ns" { sda sda~1 Selector67~491 Selector27~462 Selector27~464 Selector110~650 sda_buf } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "14.513 ns" { sda sda~1 Selector67~491 Selector27~462 Selector27~464 Selector110~650 sda_buf } { 0.000ns 0.000ns 5.612ns 0.788ns 0.765ns 1.872ns 0.714ns } { 0.000ns 1.132ns 0.914ns 0.511ns 0.511ns 0.511ns 1.183ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 29 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.357 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 79 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 79; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.307 ns) + CELL(0.918 ns) 7.357 ns sda_buf 2 REG LC_X12_Y8_N0 20 " "Info: 2: + IC(5.307 ns) + CELL(0.918 ns) = 7.357 ns; Loc. = LC_X12_Y8_N0; Fanout = 20; REG Node = 'sda_buf'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.225 ns" { clk sda_buf } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.86 % ) " "Info: Total cell delay = 2.050 ns ( 27.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.307 ns ( 72.14 % ) " "Info: Total interconnect delay = 5.307 ns ( 72.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.357 ns" { clk sda_buf } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.357 ns" { clk clk~combout sda_buf } { 0.000ns 0.000ns 5.307ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "14.513 ns" { sda sda~1 Selector67~491 Selector27~462 Selector27~464 Selector110~650 sda_buf } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "14.513 ns" { sda sda~1 Selector67~491 Selector27~462 Selector27~464 Selector110~650 sda_buf } { 0.000ns 0.000ns 5.612ns 0.788ns 0.765ns 1.872ns 0.714ns } { 0.000ns 1.132ns 0.914ns 0.511ns 0.511ns 0.511ns 1.183ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.357 ns" { clk sda_buf } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.357 ns" { clk clk~combout sda_buf } { 0.000ns 0.000ns 5.307ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg_data\[5\] en\[1\]~reg0 21.198 ns register " "Info: tco from clock \"clk\" to destination pin \"seg_data\[5\]\" through register \"en\[1\]~reg0\" is 21.198 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.357 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 79 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 79; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.307 ns) + CELL(0.918 ns) 7.357 ns en\[1\]~reg0 2 REG LC_X9_Y8_N9 8 " "Info: 2: + IC(5.307 ns) + CELL(0.918 ns) = 7.357 ns; Loc. = LC_X9_Y8_N9; Fanout = 8; REG Node = 'en\[1\]~reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.225 ns" { clk en[1]~reg0 } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 706 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.86 % ) " "Info: Total cell delay = 2.050 ns ( 27.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.307 ns ( 72.14 % ) " "Info: Total interconnect delay = 5.307 ns ( 72.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.357 ns" { clk en[1]~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.357 ns" { clk clk~combout en[1]~reg0 } { 0.000ns 0.000ns 5.307ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 706 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.465 ns + Longest register pin " "Info: + Longest register to pin delay is 13.465 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en\[1\]~reg0 1 REG LC_X9_Y8_N9 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y8_N9; Fanout = 8; REG Node = 'en\[1\]~reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { en[1]~reg0 } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 706 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.712 ns) + CELL(0.914 ns) 3.626 ns Selector136~14 2 COMB LC_X12_Y9_N4 7 " "Info: 2: + IC(2.712 ns) + CELL(0.914 ns) = 3.626 ns; Loc. = LC_X12_Y9_N4; Fanout = 7; COMB Node = 'Selector136~14'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.626 ns" { en[1]~reg0 Selector136~14 } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 711 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.715 ns) + CELL(0.740 ns) 7.081 ns WideOr5~562 3 COMB LC_X12_Y10_N6 1 " "Info: 3: + IC(2.715 ns) + CELL(0.740 ns) = 7.081 ns; Loc. = LC_X12_Y10_N6; Fanout = 1; COMB Node = 'WideOr5~562'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.455 ns" { Selector136~14 WideOr5~562 } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 723 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.138 ns) + CELL(0.740 ns) 8.959 ns WideOr5~563 4 COMB LC_X13_Y10_N6 1 " "Info: 4: + IC(1.138 ns) + CELL(0.740 ns) = 8.959 ns; Loc. = LC_X13_Y10_N6; Fanout = 1; COMB Node = 'WideOr5~563'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.878 ns" { WideOr5~562 WideOr5~563 } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 723 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.184 ns) + CELL(2.322 ns) 13.465 ns seg_data\[5\] 5 PIN PIN_111 0 " "Info: 5: + IC(2.184 ns) + CELL(2.322 ns) = 13.465 ns; Loc. = PIN_111; Fanout = 0; PIN Node = 'seg_data\[5\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.506 ns" { WideOr5~563 seg_data[5] } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.716 ns ( 35.02 % ) " "Info: Total cell delay = 4.716 ns ( 35.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.749 ns ( 64.98 % ) " "Info: Total interconnect delay = 8.749 ns ( 64.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "13.465 ns" { en[1]~reg0 Selector136~14 WideOr5~562 WideOr5~563 seg_data[5] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "13.465 ns" { en[1]~reg0 Selector136~14 WideOr5~562 WideOr5~563 seg_data[5] } { 0.000ns 2.712ns 2.715ns 1.138ns 2.184ns } { 0.000ns 0.914ns 0.740ns 0.740ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.357 ns" { clk en[1]~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.357 ns" { clk clk~combout en[1]~reg0 } { 0.000ns 0.000ns 5.307ns } { 0.000ns 1.132ns 0.918ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "13.465 ns" { en[1]~reg0 Selector136~14 WideOr5~562 WideOr5~563 seg_data[5] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "13.465 ns" { en[1]~reg0 Selector136~14 WideOr5~562 WideOr5~563 seg_data[5] } { 0.000ns 2.712ns 2.715ns 1.138ns 2.184ns } { 0.000ns 0.914ns 0.740ns 0.740ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "writeData_reg\[3\] data_in\[3\] clk 1.366 ns register " "Info: th for register \"writeData_reg\[3\]\" (data pin = \"data_in\[3\]\", clock pin = \"clk\") is 1.366 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.357 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 79 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 79; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.307 ns) + CELL(0.918 ns) 7.357 ns writeData_reg\[3\] 2 REG LC_X13_Y7_N6 2 " "Info: 2: + IC(5.307 ns) + CELL(0.918 ns) = 7.357 ns; Loc. = LC_X13_Y7_N6; Fanout = 2; REG Node = 'writeData_reg\[3\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.225 ns" { clk writeData_reg[3] } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 692 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.86 % ) " "Info: Total cell delay = 2.050 ns ( 27.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.307 ns ( 72.14 % ) " "Info: Total interconnect delay = 5.307 ns ( 72.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.357 ns" { clk writeData_reg[3] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.357 ns" { clk clk~combout writeData_reg[3] } { 0.000ns 0.000ns 5.307ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 692 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.212 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.212 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns data_in\[3\] 1 PIN PIN_67 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_67; Fanout = 1; PIN Node = 'data_in\[3\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_in[3] } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.800 ns) + CELL(0.280 ns) 6.212 ns writeData_reg\[3\] 2 REG LC_X13_Y7_N6 2 " "Info: 2: + IC(4.800 ns) + CELL(0.280 ns) = 6.212 ns; Loc. = LC_X13_Y7_N6; Fanout = 2; REG Node = 'writeData_reg\[3\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.080 ns" { data_in[3] writeData_reg[3] } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 692 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns ( 22.73 % ) " "Info: Total cell delay = 1.412 ns ( 22.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.800 ns ( 77.27 % ) " "Info: Total interconnect delay = 4.800 ns ( 77.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.212 ns" { data_in[3] writeData_reg[3] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "6.212 ns" { data_in[3] data_in[3]~combout writeData_reg[3] } { 0.000ns 0.000ns 4.800ns } { 0.000ns 1.132ns 0.280ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.357 ns" { clk writeData_reg[3] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.357 ns" { clk clk~combout writeData_reg[3] } { 0.000ns 0.000ns 5.307ns } { 0.000ns 1.132ns 0.918ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.212 ns" { data_in[3] writeData_reg[3] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "6.212 ns" { data_in[3] data_in[3]~combout writeData_reg[3] } { 0.000ns 0.000ns 4.800ns } { 0.000ns 1.132ns 0.280ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." {  } {  } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 0 0}