i2c.fit.qmsg

i2c总线的CPLD程序

{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "data_in\[4\] " "Warning: Node \"data_in\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_in\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "data_in\[5\] " "Warning: Node \"data_in\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_in\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "data_in\[6\] " "Warning: Node \"data_in\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_in\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "data_in\[7\] " "Warning: Node \"data_in\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_in\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0}  } {  } 0 0 "Ignored locations or region assignments to the following nodes" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "10.297 ns register register " "Info: Estimated most critical path is register to register delay of 10.297 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inner_state.stop 1 REG LAB_X10_Y7 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y7; Fanout = 18; REG Node = 'inner_state.stop'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { inner_state.stop } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.159 ns) + CELL(0.200 ns) 1.359 ns readData_reg\[0\]~85 2 COMB LAB_X10_Y7 5 " "Info: 2: + IC(1.159 ns) + CELL(0.200 ns) = 1.359 ns; Loc. = LAB_X10_Y7; Fanout = 5; COMB Node = 'readData_reg\[0\]~85'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.359 ns" { inner_state.stop readData_reg[0]~85 } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 692 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.382 ns) + CELL(0.200 ns) 2.941 ns Selector66~408 3 COMB LAB_X11_Y7 1 " "Info: 3: + IC(1.382 ns) + CELL(0.200 ns) = 2.941 ns; Loc. = LAB_X11_Y7; Fanout = 1; COMB Node = 'Selector66~408'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.582 ns" { readData_reg[0]~85 Selector66~408 } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 518 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.983 ns) + CELL(0.200 ns) 4.124 ns Selector66~409 4 COMB LAB_X11_Y7 1 " "Info: 4: + IC(0.983 ns) + CELL(0.200 ns) = 4.124 ns; Loc. = LAB_X11_Y7; Fanout = 1; COMB Node = 'Selector66~409'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.183 ns" { Selector66~408 Selector66~409 } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 518 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.615 ns) + CELL(0.740 ns) 6.479 ns Selector111~901 5 COMB LAB_X11_Y5 1 " "Info: 5: + IC(1.615 ns) + CELL(0.740 ns) = 6.479 ns; Loc. = LAB_X11_Y5; Fanout = 1; COMB Node = 'Selector111~901'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.355 ns" { Selector66~409 Selector111~901 } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.269 ns) + CELL(0.914 ns) 7.662 ns Selector111~903 6 COMB LAB_X11_Y5 1 " "Info: 6: + IC(0.269 ns) + CELL(0.914 ns) = 7.662 ns; Loc. = LAB_X11_Y5; Fanout = 1; COMB Node = 'Selector111~903'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.183 ns" { Selector111~901 Selector111~903 } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.740 ns) 8.845 ns Selector111~904 7 COMB LAB_X11_Y5 1 " "Info: 7: + IC(0.443 ns) + CELL(0.740 ns) = 8.845 ns; Loc. = LAB_X11_Y5; Fanout = 1; COMB Node = 'Selector111~904'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.183 ns" { Selector111~903 Selector111~904 } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.269 ns) + CELL(1.183 ns) 10.297 ns link 8 REG LAB_X11_Y5 11 " "Info: 8: + IC(0.269 ns) + CELL(1.183 ns) = 10.297 ns; Loc. = LAB_X11_Y5; Fanout = 11; REG Node = 'link'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.452 ns" { Selector111~904 link } "NODE_NAME" } } { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.177 ns ( 40.57 % ) " "Info: Total cell delay = 4.177 ns ( 40.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.120 ns ( 59.43 % ) " "Info: Total interconnect delay = 6.120 ns ( 59.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "10.297 ns" { inner_state.stop readData_reg[0]~85 Selector66~408 Selector66~409 Selector111~901 Selector111~903 Selector111~904 link } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 9 " "Info: Average interconnect usage is 5% of the available device resources. Peak interconnect usage is 9%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X9_Y0 X17_Y11 " "Info: The peak interconnect region extends from location X9_Y0 to location X17_Y11" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "2 " "Warning: Following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "lowbit GND " "Info: Pin lowbit has GND driving its datain port" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 18 -1 0 } } { "d:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "lowbit" } } } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { lowbit } "NODE_NAME" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { lowbit } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seg_data\[0\] VCC " "Info: Pin seg_data\[0\] has VCC driving its datain port" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 20 -1 0 } } { "d:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "seg_data\[0\]" } } } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { seg_data[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { seg_data[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "link " "Info: Following pins have the same output enable: link" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sda 3.3-V LVTTL " "Info: Type bidirectional pin sda uses the 3.3-V LVTTL I/O standard" {  } { { "i2c.v" "" { Text "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.v" 14 -1 0 } } { "d:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "sda" } } } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { sda } "NODE_NAME" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { sda } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "158 " "Info: Allocated 158 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jul 06 20:50:54 2008 " "Info: Processing ended: Sun Jul 06 20:50:54 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.fit.smsg " "Info: Generated suppressed messages file F:/视频监控方案/CPLD1270开发板/EDA-CoreBoard/示范程序/verilog/接口实验/i2c总线/i2c.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}