i2c.map.eqn

i2c总线的CPLD程序

--operation mode is normal

clk_div[6]_lut_out = A1L031 & (clk_div[3] # !A1L392 # !A1L292);
clk_div[6] = DFFEAS(clk_div[6]_lut_out, clk, rst, , , , , , );


--clk_div[4] is clk_div[4]
--operation mode is normal

clk_div[4]_lut_out = A1L231;
clk_div[4] = DFFEAS(clk_div[4]_lut_out, clk, rst, , , , , , );


--A1L392 is reduce_nor~278
--operation mode is normal

A1L392 = cnt_scan[1] & clk_div[6] & (!clk_div[4]);


--A1L172 is phase2~33
--operation mode is normal

A1L172 = clk_div[4] & (!cnt_scan[1] & !clk_div[6]);


--cnt_delay[18] is cnt_delay[18]
--operation mode is normal

cnt_delay[18]_lut_out = A1L431 & (A1L592 # !A1L081);
cnt_delay[18] = DFFEAS(cnt_delay[18]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[13] is cnt_delay[13]
--operation mode is normal

cnt_delay[13]_lut_out = A1L631 & (A1L592 # !A1L081);
cnt_delay[13] = DFFEAS(cnt_delay[13]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[12] is cnt_delay[12]
--operation mode is normal

cnt_delay[12]_lut_out = A1L831 & (A1L592 # !A1L081);
cnt_delay[12] = DFFEAS(cnt_delay[12]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[10] is cnt_delay[10]
--operation mode is normal

cnt_delay[10]_lut_out = A1L041 & (A1L592 # !A1L081);
cnt_delay[10] = DFFEAS(cnt_delay[10]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L492 is reduce_nor~279
--operation mode is normal

A1L492 = !cnt_delay[10] # !cnt_delay[12] # !cnt_delay[13] # !cnt_delay[18];


--cnt_delay[8] is cnt_delay[8]
--operation mode is normal

cnt_delay[8]_lut_out = A1L241 & (A1L592 # !A1L081);
cnt_delay[8] = DFFEAS(cnt_delay[8]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[19] is cnt_delay[19]
--operation mode is normal

cnt_delay[19]_lut_out = A1L441 & (A1L592 # !A1L081);
cnt_delay[19] = DFFEAS(cnt_delay[19]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L592 is reduce_nor~280
--operation mode is normal

A1L592 = A1L492 # !cnt_delay[19] # !cnt_delay[8];


--cnt_delay[17] is cnt_delay[17]
--operation mode is normal

cnt_delay[17]_lut_out = A1L541;
cnt_delay[17] = DFFEAS(cnt_delay[17]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[16] is cnt_delay[16]
--operation mode is normal

cnt_delay[16]_lut_out = A1L741;
cnt_delay[16] = DFFEAS(cnt_delay[16]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[15] is cnt_delay[15]
--operation mode is normal

cnt_delay[15]_lut_out = A1L941;
cnt_delay[15] = DFFEAS(cnt_delay[15]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[14] is cnt_delay[14]
--operation mode is normal

cnt_delay[14]_lut_out = A1L151;
cnt_delay[14] = DFFEAS(cnt_delay[14]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L671 is always2~176
--operation mode is normal

A1L671 = !cnt_delay[17] & !cnt_delay[16] & !cnt_delay[15] & !cnt_delay[14];


--cnt_delay[11] is cnt_delay[11]
--operation mode is normal

cnt_delay[11]_lut_out = A1L351;
cnt_delay[11] = DFFEAS(cnt_delay[11]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[9] is cnt_delay[9]
--operation mode is normal

cnt_delay[9]_lut_out = A1L551;
cnt_delay[9] = DFFEAS(cnt_delay[9]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[7] is cnt_delay[7]
--operation mode is normal

cnt_delay[7]_lut_out = A1L751;
cnt_delay[7] = DFFEAS(cnt_delay[7]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[6] is cnt_delay[6]
--operation mode is normal

cnt_delay[6]_lut_out = A1L951;
cnt_delay[6] = DFFEAS(cnt_delay[6]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L771 is always2~177
--operation mode is normal

A1L771 = !cnt_delay[11] & !cnt_delay[9] & !cnt_delay[7] & !cnt_delay[6];


--cnt_delay[5] is cnt_delay[5]
--operation mode is normal

cnt_delay[5]_lut_out = A1L161;
cnt_delay[5] = DFFEAS(cnt_delay[5]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[4] is cnt_delay[4]
--operation mode is normal

cnt_delay[4]_lut_out = A1L361;
cnt_delay[4] = DFFEAS(cnt_delay[4]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[3] is cnt_delay[3]
--operation mode is normal

cnt_delay[3]_lut_out = A1L561;
cnt_delay[3] = DFFEAS(cnt_delay[3]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[2] is cnt_delay[2]
--operation mode is normal

cnt_delay[2]_lut_out = A1L761;
cnt_delay[2] = DFFEAS(cnt_delay[2]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L871 is always2~178
--operation mode is normal

A1L871 = !cnt_delay[5] & !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[2];


--cnt_delay[1] is cnt_delay[1]
--operation mode is normal

cnt_delay[1]_lut_out = A1L961;
cnt_delay[1] = DFFEAS(cnt_delay[1]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[0] is cnt_delay[0]
--operation mode is normal

cnt_delay[0]_lut_out = A1L171 & (A1L592 # !A1L081);
cnt_delay[0] = DFFEAS(cnt_delay[0]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L971 is always2~179
--operation mode is normal

A1L971 = !cnt_delay[1] & !cnt_delay[0];


--A1L081 is always2~180
--operation mode is normal

A1L081 = A1L671 & A1L771 & A1L871 & A1L971;


--A1L1 is Select~18569
--operation mode is normal

A1L1 = !rd_input # !wr_input;


--A1L2 is Select~18570
--operation mode is normal

A1L2 = !main_state.00 & (A1L592 # !A1L1 # !A1L081);


--main_state.01 is main_state.01
--operation mode is normal

main_state.01_lut_out = !A1L011 & (A1L11 & (!wr_input) # !A1L11 & A1L43);
main_state.01 = DFFEAS(main_state.01_lut_out, clk, rst, , , , , , );


--i2c_state.read_ini is i2c_state.read_ini
--operation mode is normal

i2c_state.read_ini_lut_out = main_state.10 & (A1L81 # i2c_state.read_ini & A1L53) # !main_state.10 & i2c_state.read_ini & A1L53;
i2c_state.read_ini = DFFEAS(i2c_state.read_ini_lut_out, clk, rst, , , , , , );


--A1L692 is reduce_nor~281
--operation mode is normal

A1L692 = i2c_state.read_data # i2c_state.read_ini;


--i2c_state.sendaddr is i2c_state.sendaddr
--operation mode is normal

i2c_state.sendaddr_lut_out = A1L63 # main_state.10 & i2c_state.sendaddr & !A1L61;
i2c_state.sendaddr = DFFEAS(i2c_state.sendaddr_lut_out, clk, rst, , , , , , );


--i2c_state.ini is i2c_state.ini
--operation mode is normal

i2c_state.ini_lut_out = main_state.10 & (i2c_state.ini # !A1L73) # !main_state.10 & main_state.01 & (i2c_state.ini # !A1L73);
i2c_state.ini = DFFEAS(i2c_state.ini_lut_out, clk, rst, , , , , , );


--A1L3 is Select~18571
--operation mode is normal

A1L3 = inner_state.ack & (i2c_state.read_ini # i2c_state.sendaddr # !i2c_state.ini);


--A1L4 is Select~18572
--operation mode is normal

A1L4 = A1L021 & (A1L382 & inner_state.stop # !A1L382 & (phase1));


--i2c_state.write_data is i2c_state.write_data
--operation mode is normal

i2c_state.write_data_lut_out = main_state.01 & (i2c_state.write_data # A1L81) # !main_state.01 & i2c_state.write_data & main_state.10;
i2c_state.write_data = DFFEAS(i2c_state.write_data_lut_out, clk, rst, , , , , , );


--A1L5 is Select~18573
--operation mode is normal

A1L5 = main_state.01 & (A1L692 # i2c_state.write_data & !inner_state.ack);


--A1L6 is Select~18574
--operation mode is normal

A1L6 = A1L4 # inner_state.stop & A1L5 & !A1L692;


--phase3 is phase3
--operation mode is normal

phase3_lut_out = phase3 # !A1L782;
phase3 = DFFEAS(phase3_lut_out, clk, rst, , , , , phase3, );


--A1L7 is Select~18575
--operation mode is normal

A1L7 = main_state.10 & (!i2c_state.read_data) # !main_state.10 & (!i2c_state.write_data # !inner_state.stop);


--sda_buf is sda_buf
--operation mode is normal

sda_buf_lut_out = !A1L56 & !A1L64 & !A1L17 # !A1L16;
sda_buf = DFFEAS(sda_buf_lut_out, clk, rst, , , , , , );


--A1L8 is Select~18576
--operation mode is normal

A1L8 = main_state.00 & (A1L7 & (!sda_buf) # !A1L7 & phase3);


--A1L121 is add~549
--operation mode is arithmetic

A1L121 = !clk_div[0];

--A1L221 is add~551
--operation mode is arithmetic

A1L221 = CARRY(clk_div[0]);


--A1L792 is reduce_nor~282
--operation mode is normal

A1L792 = !clk_div[0] & !clk_div[7] & !clk_div[2] & !clk_div[5];


--A1L682 is reduce_nor~1
--operation mode is normal

A1L682 = !A1L792 # !A1L172 # !clk_div[3];


--A1L9 is Select~18578
--operation mode is normal

A1L9 = !inner_state.stop # !phase3;


--A1L01 is Select~18579
--operation mode is normal

A1L01 = i2c_state.read_data & A1L9 # !i2c_state.read_data & (sda_buf # !phase1);


--A1L11 is Select~18580
--operation mode is normal

A1L11 = A1L081 & A1L1 & !main_state.00 & !A1L592;


--A1L052 is i2c_state~115
--operation mode is normal

A1L052 = phase3 & inner_state.ack;


--A1L21 is Select~18582
--operation mode is normal

A1L21 = main_state.10 & i2c_state.read_ini;


--A1L31 is Select~18583
--operation mode is normal

A1L31 = main_state.10 # main_state.01;


--link is link
--operation mode is normal

link_lut_out = A1L18 # A1L28 # A1L03 & A1L48;
link = DFFEAS(link_lut_out, clk, rst, , , , , , );


--A1L571 is always2~2
--operation mode is normal

A1L571 = phase3 & link;


--A1L41 is Select~18585
--operation mode is normal

A1L41 = !inner_state.start & (i2c_state.ini # !A1L571) # !main_state.01;


--A1L51 is Select~18586
--operation mode is normal

A1L51 = i2c_state.read_ini & (!link # !phase3) # !i2c_state.read_ini & !i2c_state.ini & (!link # !phase3);


--A1L61 is Select~18587
--operation mode is normal

A1L61 = !i2c_state.read_data & !i2c_state.write_data;


--A1L71 is Select~18588
--operation mode is normal

A1L71 = !inner_state.start & (i2c_state.sendaddr # A1L51 # !A1L61);


--A1L81 is Select~18589
--operation mode is normal

A1L81 = phase3 & inner_state.ack & i2c_state.sendaddr;


--A1L91 is Select~18591
--operation mode is normal

A1L91 = A1L382 # main_state.01 & i2c_state.write_data & !phase1;


--inner_state.eighth is inner_state.eighth
--operation mode is normal

inner_state.eighth_lut_out = A1L68 # A1L78 # inner_state.eighth & A1L09;
inner_state.eighth = DFFEAS(inner_state.eighth_lut_out, clk, rst, , , , , , );


--A1L02 is Select~18593
--operation mode is normal

A1L02 = i2c_state.read_data # i2c_state.sendaddr;


--A1L12 is Select~18594
--operation mode is normal

A1L12 = A1L211 & inner_state.eighth # !A1L211 & (inner_state.ack);


--A1L22 is Select~18595
--operation mode is normal

A1L22 = main_state.10 & (i2c_state.write_data & inner_state.ack # !i2c_state.write_data & (A1L12));


--A1L32 is Select~18596
--operation mode is normal

A1L32 = i2c_state.write_data & inner_state.eighth;


--A1L42 is Select~18597
--operation mode is normal

A1L42 = main_state.01 & A1L32 & (phase3 # inner_state.ack);


--A1L52 is Select~18598
--operation mode is normal

A1L52 = inner_state.eighth # A1L482 & (!inner_state.ack # !phase1);


--A1L62 is Select~18599
--operation mode is normal

A1L62 = i2c_state.write_data & (A1L52 # !i2c_state.ini & !i2c_state.sendaddr) # !i2c_state.write_data & (!i2c_state.ini & !i2c_state.sendaddr);


--A1L72 is Select~18600
--operation mode is normal

A1L72 = i2c_state.sendaddr # i2c_state.write_data & A1L52;


--A1L82 is Select~18601
--operation mode is normal

A1L82 = A1L62 & (inner_state.ack $ (inner_state.eighth & !A1L311)) # !A1L62 & A1L311 & (inner_state.eighth $ inner_state.ack);


--A1L92 is Select~18602
--operation mode is normal

A1L92 = inner_state.ack $ (phase3 & A1L82);


--A1L03 is Select~18603
--operation mode is normal

A1L03 = main_state.01 & (!inner_state.eighth # !i2c_state.write_data);


--A1L321 is add~554
--operation mode is arithmetic

A1L321_carry_eqn = A1L921;
A1L321 = clk_div[3] $ (A1L321_carry_eqn);

--A1L421 is add~556
--operation mode is arithmetic

A1L421 = CARRY(!A1L921 # !clk_div[3]);


--A1L521 is add~559
--operation mode is arithmetic

A1L521_carry_eqn = A1L331;
A1L521 = clk_div[5] $ (A1L521_carry_eqn);

--A1L621 is add~561
--operation mode is arithmetic

A1L621 = CARRY(!A1L331 # !clk_div[5]);


--A1L721 is add~564
--operation mode is normal

A1L721_carry_eqn = A1L131;
A1L721 = clk_div[7] $ (A1L721_carry_eqn);