📄 i2c.map.rpt
字号:
+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |i2c ;
+----------------+--------+-------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+--------+-------------------------------------------+
; div_parameter ; 100 ; Signed Integer ;
; start ; 0000 ; Unsigned Binary ;
; first ; 0001 ; Unsigned Binary ;
; second ; 0010 ; Unsigned Binary ;
; third ; 0011 ; Unsigned Binary ;
; fourth ; 0100 ; Unsigned Binary ;
; fifth ; 0101 ; Unsigned Binary ;
; sixth ; 0110 ; Unsigned Binary ;
; seventh ; 0111 ; Unsigned Binary ;
; eighth ; 1000 ; Unsigned Binary ;
; ack ; 1001 ; Unsigned Binary ;
; stop ; 1010 ; Unsigned Binary ;
; ini ; 000 ; Unsigned Binary ;
; sendaddr ; 001 ; Unsigned Binary ;
; write_data ; 010 ; Unsigned Binary ;
; read_data ; 011 ; Unsigned Binary ;
; read_ini ; 000100 ; Unsigned Binary ;
+----------------+--------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
Info: Processing started: Sun Jul 06 20:50:43 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off i2c -c i2c
Info: Found 1 design units, including 1 entities, in source file i2c.v
Info: Found entity 1: i2c
Info: Elaborating entity "i2c" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at i2c.v(72): truncated value with size 32 to match size of target (20)
Warning (10230): Verilog HDL assignment warning at i2c.v(90): truncated value with size 32 to match size of target (8)
Info (10264): Verilog HDL Case Statement information at i2c.v(155): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at i2c.v(231): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at i2c.v(296): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at i2c.v(153): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at i2c.v(377): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at i2c.v(453): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at i2c.v(518): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at i2c.v(593): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at i2c.v(375): all case item expressions in this case statement are onehot
Warning (10240): Verilog HDL Always Construct warning at i2c.v(114): inferring latch(es) for variable "addr", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at i2c.v(40): inferred latch for "addr[7]"
Info (10041): Verilog HDL or VHDL info at i2c.v(40): inferred latch for "addr[6]"
Info (10041): Verilog HDL or VHDL info at i2c.v(40): inferred latch for "addr[5]"
Info (10041): Verilog HDL or VHDL info at i2c.v(40): inferred latch for "addr[4]"
Info (10041): Verilog HDL or VHDL info at i2c.v(40): inferred latch for "addr[3]"
Info (10041): Verilog HDL or VHDL info at i2c.v(40): inferred latch for "addr[2]"
Info (10041): Verilog HDL or VHDL info at i2c.v(40): inferred latch for "addr[1]"
Info (10041): Verilog HDL or VHDL info at i2c.v(40): inferred latch for "addr[0]"
Warning (10230): Verilog HDL assignment warning at i2c.v(703): truncated value with size 32 to match size of target (12)
Info (10264): Verilog HDL Case Statement information at i2c.v(711): all case item expressions in this case statement are onehot
Warning: Reduced register "writeData_reg[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "writeData_reg[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "writeData_reg[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "writeData_reg[4]" with stuck data_in port to stuck value GND
Info: State machine "|i2c|main_state" contains 3 states
Info: State machine "|i2c|i2c_state" contains 5 states
Info: State machine "|i2c|inner_state" contains 11 states
Info: Selected Auto state machine encoding method for state machine "|i2c|main_state"
Info: Encoding result for state machine "|i2c|main_state"
Info: Completed encoding using 3 state bits
Info: Encoded state bit "main_state.00"
Info: Encoded state bit "main_state.10"
Info: Encoded state bit "main_state.01"
Info: State "|i2c|main_state.00" uses code string "000"
Info: State "|i2c|main_state.01" uses code string "101"
Info: State "|i2c|main_state.10" uses code string "110"
Info: Selected Auto state machine encoding method for state machine "|i2c|i2c_state"
Info: Encoding result for state machine "|i2c|i2c_state"
Info: Completed encoding using 5 state bits
Info: Encoded state bit "i2c_state.read_data"
Info: Encoded state bit "i2c_state.sendaddr"
Info: Encoded state bit "i2c_state.write_data"
Info: Encoded state bit "i2c_state.ini"
Info: Encoded state bit "i2c_state.read_ini"
Info: State "|i2c|i2c_state.ini" uses code string "00000"
Info: State "|i2c|i2c_state.read_ini" uses code string "00011"
Info: State "|i2c|i2c_state.write_data" uses code string "00110"
Info: State "|i2c|i2c_state.sendaddr" uses code string "01010"
Info: State "|i2c|i2c_state.read_data" uses code string "10010"
Info: Selected Auto state machine encoding method for state machine "|i2c|inner_state"
Info: Encoding result for state machine "|i2c|inner_state"
Info: Completed encoding using 11 state bits
Info: Encoded state bit "inner_state.stop"
Info: Encoded state bit "inner_state.first"
Info: Encoded state bit "inner_state.second"
Info: Encoded state bit "inner_state.third"
Info: Encoded state bit "inner_state.fourth"
Info: Encoded state bit "inner_state.fifth"
Info: Encoded state bit "inner_state.sixth"
Info: Encoded state bit "inner_state.seventh"
Info: Encoded state bit "inner_state.eighth"
Info: Encoded state bit "inner_state.ack"
Info: Encoded state bit "inner_state.start"
Info: State "|i2c|inner_state.start" uses code string "00000000000"
Info: State "|i2c|inner_state.ack" uses code string "00000000011"
Info: State "|i2c|inner_state.eighth" uses code string "00000000101"
Info: State "|i2c|inner_state.seventh" uses code string "00000001001"
Info: State "|i2c|inner_state.sixth" uses code string "00000010001"
Info: State "|i2c|inner_state.fifth" uses code string "00000100001"
Info: State "|i2c|inner_state.fourth" uses code string "00001000001"
Info: State "|i2c|inner_state.third" uses code string "00010000001"
Info: State "|i2c|inner_state.second" uses code string "00100000001"
Info: State "|i2c|inner_state.first" uses code string "01000000001"
Info: State "|i2c|inner_state.stop" uses code string "10000000001"
Info: Duplicate registers merged to single register
Info: Duplicate register "clk_div[0]" merged to single register "cnt_scan[0]"
Info: Duplicate register "clk_div[1]" merged to single register "cnt_scan[1]"
Warning: Output pins are stuck at VCC or GND
Warning: Pin "lowbit" stuck at GND
Warning: Pin "seg_data[0]" stuck at VCC
Info: Registers with preset signals will power-up high
Info: 6 registers lost all their fanouts during netlist optimizations. The first 6 are displayed below.
Info: Register "i2c_state~65" lost all its fanouts during netlist optimizations.
Info: Register "i2c_state~66" lost all its fanouts during netlist optimizations.
Info: Register "inner_state~140" lost all its fanouts during netlist optimizations.
Info: Register "inner_state~141" lost all its fanouts during netlist optimizations.
Info: Register "inner_state~142" lost all its fanouts during netlist optimizations.
Info: Register "inner_state~143" lost all its fanouts during netlist optimizations.
Info: Implemented 296 device resources after synthesis - the final resource count might be different
Info: Implemented 8 input pins
Info: Implemented 12 output pins
Info: Implemented 1 bidirectional pins
Info: Implemented 275 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
Info: Allocated 125 megabytes of memory during processing
Info: Processing ended: Sun Jul 06 20:50:47 2008
Info: Elapsed time: 00:00:04
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -