i2c.tan.rpt

i2c总线的CPLD程序

; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; fmax Requirement                                      ; 45 MHz             ;      ;    ;             ;
; Ignore Clock Settings                                 ; On                 ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; 45.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                     ;
+-----------------------------------------+-----------------------------------------------------+----------------------+---------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                 ; To                  ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------+---------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 10.190 ns                               ; 83.11 MHz ( period = 12.032 ns )                    ; inner_state.stop     ; link                ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 11.323 ns               ;
; 10.352 ns                               ; 84.25 MHz ( period = 11.870 ns )                    ; inner_state.start    ; link                ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 11.161 ns               ;
; 10.707 ns                               ; 86.84 MHz ( period = 11.515 ns )                    ; inner_state.eighth   ; link                ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 10.806 ns               ;
; 10.796 ns                               ; 87.52 MHz ( period = 11.426 ns )                    ; inner_state.second   ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 10.717 ns               ;
; 10.900 ns                               ; 88.32 MHz ( period = 11.322 ns )                    ; inner_state.seventh  ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 10.613 ns               ;
; 11.047 ns                               ; 89.49 MHz ( period = 11.175 ns )                    ; inner_state.ack      ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 10.466 ns               ;
; 11.051 ns                               ; 89.52 MHz ( period = 11.171 ns )                    ; inner_state.first    ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 10.462 ns               ;
; 11.186 ns                               ; 90.61 MHz ( period = 11.036 ns )                    ; inner_state.stop     ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 10.327 ns               ;
; 11.310 ns                               ; 91.64 MHz ( period = 10.912 ns )                    ; phase1               ; link                ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 10.203 ns               ;
; 11.387 ns                               ; 92.29 MHz ( period = 10.835 ns )                    ; inner_state.ack      ; link                ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 10.126 ns               ;
; 11.471 ns                               ; 93.01 MHz ( period = 10.751 ns )                    ; inner_state.start    ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 10.042 ns               ;
; 11.561 ns                               ; 93.80 MHz ( period = 10.661 ns )                    ; inner_state.eighth   ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.952 ns                ;
; 11.574 ns                               ; 93.91 MHz ( period = 10.648 ns )                    ; sda_buf              ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.939 ns                ;
; 11.673 ns                               ; 94.80 MHz ( period = 10.549 ns )                    ; inner_state.fifth    ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.840 ns                ;
; 11.699 ns                               ; 95.03 MHz ( period = 10.523 ns )                    ; i2c_state.write_data ; link                ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.814 ns                ;
; 11.727 ns                               ; 95.28 MHz ( period = 10.495 ns )                    ; inner_state.fourth   ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.786 ns                ;
; 11.748 ns                               ; 95.47 MHz ( period = 10.474 ns )                    ; inner_state.sixth    ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.765 ns                ;
; 11.821 ns                               ; 96.14 MHz ( period = 10.401 ns )                    ; inner_state.third    ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.692 ns                ;
; 11.876 ns                               ; 96.66 MHz ( period = 10.346 ns )                    ; writeData_reg[0]     ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.637 ns                ;
; 11.912 ns                               ; 96.99 MHz ( period = 10.310 ns )                    ; i2c_state.ini        ; link                ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.601 ns                ;
; 11.939 ns                               ; 97.25 MHz ( period = 10.283 ns )                    ; writeData_reg[3]     ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.574 ns                ;
; 11.966 ns                               ; 97.50 MHz ( period = 10.256 ns )                    ; link                 ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.547 ns                ;
; 12.057 ns                               ; 98.38 MHz ( period = 10.165 ns )                    ; phase0               ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.456 ns                ;
; 12.075 ns                               ; 98.55 MHz ( period = 10.147 ns )                    ; writeData_reg[2]     ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.438 ns                ;
; 12.108 ns                               ; 98.87 MHz ( period = 10.114 ns )                    ; i2c_state.sendaddr   ; link                ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.405 ns                ;
; 12.140 ns                               ; 99.19 MHz ( period = 10.082 ns )                    ; inner_state.stop     ; inner_state.ack     ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.373 ns                ;
; 12.185 ns                               ; 99.63 MHz ( period = 10.037 ns )                    ; i2c_state.read_data  ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.328 ns                ;
; 12.302 ns                               ; 100.81 MHz ( period = 9.920 ns )                    ; inner_state.start    ; inner_state.ack     ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.211 ns                ;
; 12.322 ns                               ; 101.01 MHz ( period = 9.900 ns )                    ; phase3               ; sda_buf             ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.191 ns                ;
; 12.325 ns                               ; 101.04 MHz ( period = 9.897 ns )                    ; i2c_state.read_data  ; inner_state.sixth   ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.188 ns                ;
; 12.384 ns                               ; 101.65 MHz ( period = 9.838 ns )                    ; i2c_state.sendaddr   ; inner_state.first   ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.129 ns                ;
; 12.409 ns                               ; 101.91 MHz ( period = 9.813 ns )                    ; cnt_delay[6]         ; main_state.01       ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 9.104 ns                ;
; 12.578 ns                               ; 103.69 MHz ( period = 9.644 ns )                    ; i2c_state.read_data  ; inner_state.first   ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.935 ns                ;
; 12.627 ns                               ; 104.22 MHz ( period = 9.595 ns )                    ; inner_state.stop     ; inner_state.sixth   ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.886 ns                ;
; 12.657 ns                               ; 104.55 MHz ( period = 9.565 ns )                    ; inner_state.eighth   ; inner_state.ack     ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.856 ns                ;
; 12.661 ns                               ; 104.59 MHz ( period = 9.561 ns )                    ; i2c_state.read_ini   ; inner_state.sixth   ; clk        ; clk      ; 22.222 ns                   ; 21.513 ns                 ; 8.852 ns                ;