📄 loadm_c.lst
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618 1 M3_25A=0x43;
619 1 M3_25B=0x45;
620 1 M3_25C=0x20;
621 1 M3_25D=0x20;
622 1 M3_25E=0x20;
623 1 M3_25F=0x20;
624 1
625 1 M3_350=0xE0;
626 1 M3_351=0x57;
627 1 M3_352=0x47;
628 1 M3_353=0x20;
629 1 M3_354=0x4C;
630 1 M3_355=0x50;
631 1 M3_356=0x2D;
632 1 M3_357=0x54;
633 1 M3_358=0x52;
634 1 M3_359=0x41;
635 1 M3_35A=0x43;
636 1 M3_35B=0x45;
637 1 M3_35C=0x20;
638 1 M3_35D=0x20;
639 1 M3_35E=0x20;
640 1 M3_35F=0x20;
641 1
642 1 M3_450=0xE0;
643 1 M3_451=0x57;
644 1 M3_452=0x47;
645 1 M3_453=0x20;
646 1 M3_454=0x4C;
647 1 M3_455=0x50;
648 1 M3_456=0x2D;
649 1 M3_457=0x54;
650 1 M3_458=0x52;
651 1 M3_459=0x41;
652 1 M3_45A=0x43;
653 1 M3_45B=0x45;
654 1 M3_45C=0x20;
655 1 M3_45D=0x20;
656 1 M3_45E=0x20;
657 1 M3_45F=0x20;
658 1
659 1 // TCnEN =0
660 1 M3_051=M3_051&0xEF;
661 1 M3_081=M3_081&0xEF;
662 1 M3_0B1=M3_0B1&0xEF;
663 1 M3_0E1=M3_0E1&0xEF;
664 1
665 1 M3_010=M3_010|0x10;//B ADD BUS HIGH IMPEDANCE
666 1 M3_011=M3_011|0x10; //LATEN=1
667 1
668 1 M3_04A=M3_04A|0x44;//T3SEL0=1;
669 1 M3_04A=M3_04A&0x5F; //T3SEL1=0,R3SEL=0; Single Undirectional Ring Mode
670 1 M3_07A=M3_07A|0x44;//T3SEL0=1;
671 1 M3_07A=M3_07A&0x5F; //T3SEL1=0,R3SEL=0; Single Undirectional Ring Mode
672 1 M3_0AA=M3_0AA|0x44;//T3SEL0=1;
673 1 M3_0AA=M3_0AA&0x5F; //T3SEL1=0,R3SEL=0; Single Undirectional Ring Mode
C51 COMPILER V7.02b LOADM_C 01/18/2005 21:37:57 PAGE 12
674 1 M3_0DA=M3_0DA|0x44;//T3SEL0=1;
675 1 M3_0DA=M3_0DA&0x5F; //T3SEL1=0,R3SEL=0; Single Undirectional Ring Mode
676 1
677 1 M3_04C=0x00;//RTUN1
678 1 M3_04D=0x00;//TTUN1
679 1 M3_04A=M3_04A&0xFD; //RnEN=0
680 1 M3_07C=0x00;//RTUN2
681 1 M3_07D=0x00;//TTUN2
682 1 M3_07A=M3_07A&0xFD; //RnEN=0
683 1 M3_0AC=0x00;
684 1 M3_0AD=0x00;
685 1 M3_0AA=M3_0AA&0xFD; //RnEN=0
686 1 M3_0DC=0x00;
687 1 M3_0DD=0x00;
688 1 M3_0DA=M3_0DA&0xFD; //RnEN=0
689 1
690 1 }
691
692 void LoadM4_C()
693 {
694 1 //INTERNAL PROCESSOR(SPOT)
695 1 M4_005=0x00;
696 1 M4_006=0x00;
697 1 M4_007=0x00;
698 1 M4_008=0x00;
699 1
700 1 //CONTROL DESCRIPTIONS
701 1 M4_010=0xC0;//MOD1=MOD0=1,AAHZE=BAHZE=0,BLOCK=0,NPIA=NPIB=NPIC=0
702 1 M4_011=0xDD;//SBTEN=1,DRPBT=1(DROP MODE),ABD=0,LATEN=1,TAISE=1,RAISE=0,TCLKI=1(时钟上升沿）,RCLKI=1(时钟
-下降沿)
703 1 M4_012=0x29;//IPOS=1,INEG=0,RFIE=1(使RFI产生中断）
704 1 M4_013=0x12;//HEAISE=0,DV1SEL=0,DV1REF=0,RDIEN=1,UQAE=1 ,TOBWZ=1
705 1
706 1 M4_055=0x02; //c2=02
707 1 M4_085=0x02;
708 1 M4_0B5=0x02;
709 1 M4_0E5=0x02;
710 1 // M4_058=0x80; //k4=08
711 1
712 1 //PROVISIONING DESCRIPTIONS
713 1 M4_014=0x13;//UEAME=1,SE1AIS=0,!!!!!!!!! PTALTE=1,HDWIE=1
714 1
715 1 M4_049=0x59;
716 1 M4_079=0x59;
717 1 M4_0A9=0x59;
718 1 M4_0D9=0x59;
719 1
720 1 //TnSEL1,TnSEL0,RnSEL,ByPass
721 1 M4_04A=M4_04A|0x44;
722 1 M4_07A=M4_07A|0x44;
723 1 M4_0AA=M4_0AA|0x44;
724 1 M4_0DA=M4_0DA|0x44;
725 1
726 1 M4_04B=0xF0;
727 1 M4_07B=0xF0;
728 1 M4_0AB=0xF0;
729 1 M4_0DB=0xF0;
730 1
731 1 M4_0F1=M4_0F1|0x08; //V4EN=1
732 1
733 1 //1BnRDI=1---SINGLE BIT RDI;J2nTEN=1,J2nSIZE=0,J2nCOM=1,J2nAISE=1(Enable ALARM CREATED BY J2)
734 1 M4_048=0x1B;
C51 COMPILER V7.02b LOADM_C 01/18/2005 21:37:57 PAGE 13
735 1 M4_078=0x1B;
736 1 M4_0A8=0x1B;
737 1 M4_0D8=0x1B;
738 1
739 1 //A Drop Bus Port n MicroProcessor-written SIGNAL LABEL =0X02
740 1 M4_053=0x02;
741 1 M4_083=0x02;
742 1 M4_0B3=0x02;
743 1 M4_0E3=0x02;
744 1
745 1 //Transmit J2 赋值
746 1 M4_540=0xE0;
747 1 M4_541=0x57;
748 1 M4_542=0x47;
749 1 M4_543=0x20;
750 1 M4_544=0x4C;
751 1 M4_545=0x50;
752 1 M4_546=0x2D;
753 1 M4_547=0x54;
754 1 M4_548=0x52;
755 1 M4_549=0x41;
756 1 M4_54A=0x43;
757 1 M4_54B=0x45;
758 1 M4_54C=0x20;
759 1 M4_54D=0x20;
760 1 M4_54E=0x20;
761 1 M4_54F=0x20;
762 1
763 1 M4_5C0=0xE0;
764 1 M4_5C1=0x57;
765 1 M4_5C2=0x47;
766 1 M4_5C3=0x20;
767 1 M4_5C4=0x4C;
768 1 M4_5C5=0x50;
769 1 M4_5C6=0x2D;
770 1 M4_5C7=0x54;
771 1 M4_5C8=0x52;
772 1 M4_5C9=0x41;
773 1 M4_5CA=0x43;
774 1 M4_5CB=0x45;
775 1 M4_5CC=0x20;
776 1 M4_5CD=0x20;
777 1 M4_5CE=0x20;
778 1 M4_5CF=0x20;
779 1
780 1 M4_640=0xE0;
781 1 M4_641=0x57;
782 1 M4_642=0x47;
783 1 M4_643=0x20;
784 1 M4_644=0x4C;
785 1 M4_645=0x50;
786 1 M4_646=0x2D;
787 1 M4_647=0x54;
788 1 M4_648=0x52;
789 1 M4_649=0x41;
790 1 M4_64A=0x43;
791 1 M4_64B=0x45;
792 1 M4_64C=0x20;
793 1 M4_64D=0x20;
794 1 M4_64E=0x20;
795 1 M4_64F=0x20;
796 1
C51 COMPILER V7.02b LOADM_C 01/18/2005 21:37:57 PAGE 14
797 1 M4_6C0=0xE0;
798 1 M4_6C1=0x57;
799 1 M4_6C2=0x47;
800 1 M4_6C3=0x20;
801 1 M4_6C4=0x4C;
802 1 M4_6C5=0x50;
803 1 M4_6C6=0x2D;
804 1 M4_6C7=0x54;
805 1 M4_6C8=0x52;
806 1 M4_6C9=0x41;
807 1 M4_6CA=0x43;
808 1 M4_6CB=0x45;
809 1 M4_6CC=0x20;
810 1 M4_6CD=0x20;
811 1 M4_6CE=0x20;
812 1 M4_6CF=0x20;
813 1
814 1 //A side Microprocessor-Written Received J2 赋值
815 1 M4_150=0xE0;
816 1 M4_151=0x57;
817 1 M4_152=0x47;
818 1 M4_153=0x20;
819 1 M4_154=0x4C;
820 1 M4_155=0x50;
821 1 M4_156=0x2D;
822 1 M4_157=0x54;
823 1 M4_158=0x52;
824 1 M4_159=0x41;
825 1 M4_15A=0x43;
826 1 M4_15B=0x45;
827 1 M4_15C=0x20;
828 1 M4_15D=0x20;
829 1 M4_15E=0x20;
830 1 M4_15F=0x20;
831 1
832 1 M4_250=0xE0;
833 1 M4_251=0x57;
834 1 M4_252=0x47;
835 1 M4_253=0x20;
836 1 M4_254=0x4C;
837 1 M4_255=0x50;
838 1 M4_256=0x2D;
839 1 M4_257=0x54;
840 1 M4_258=0x52;
841 1 M4_259=0x41;
842 1 M4_25A=0x43;
843 1 M4_25B=0x45;
844 1 M4_25C=0x20;
845 1 M4_25D=0x20;
846 1 M4_25E=0x20;
847 1 M4_25F=0x20;
848 1
849 1 M4_350=0xE0;
850 1 M4_351=0x57;
851 1 M4_352=0x47;
852 1 M4_353=0x20;
853 1 M4_354=0x4C;
854 1 M4_355=0x50;
855 1 M4_356=0x2D;
856 1 M4_357=0x54;
857 1 M4_358=0x52;
858 1 M4_359=0x41;
C51 COMPILER V7.02b LOADM_C 01/18/2005 21:37:57 PAGE 15
859 1 M4_35A=0x43;
860 1 M4_35B=0x45;
861 1 M4_35C=0x20;
862 1 M4_35D=0x20;
863 1 M4_35E=0x20;
864 1 M4_35F=0x20;
865 1
866 1 M4_450=0xE0;
867 1 M4_451=0x57;
868 1 M4_452=0x47;
869 1 M4_453=0x20;
870 1 M4_454=0x4C;
871 1 M4_455=0x50;
872 1 M4_456=0x2D;
873 1 M4_457=0x54;
874 1 M4_458=0x52;
875 1 M4_459=0x41;
876 1 M4_45A=0x43;
877 1 M4_45B=0x45;
878 1 M4_45C=0x20;
879 1 M4_45D=0x20;
880 1 M4_45E=0x20;
881 1 M4_45F=0x20;
882 1
883 1 // TCnEN =0
884 1 M4_051=M4_051&0xEF;
885 1 M4_081=M4_081&0xEF;
886 1 M4_0B1=M4_0B1&0xEF;
887 1 M4_0E1=M4_0E1&0xEF;
888 1
889 1 M4_010=M4_010|0x10;//B ADD BUS HIGH IMPEDANCE
890 1 M4_011=M4_011|0x10; //LATEN=1
891 1
892 1 M4_04A=M4_04A|0x44;//T3SEL0=1;
893 1 M4_04A=M4_04A&0x5F; //T3SEL1=0,R3SEL=0; Single Undirectional Ring Mode
894 1 M4_07A=M4_07A|0x44;//T3SEL0=1;
895 1 M4_07A=M4_07A&0x5F; //T3SEL1=0,R3SEL=0; Single Undirectional Ring Mode
896 1 M4_0AA=M4_0AA|0x44;//T3SEL0=1;
897 1 M4_0AA=M4_0AA&0x5F; //T3SEL1=0,R3SEL=0; Single Undirectional Ring Mode
898 1 M4_0DA=M4_0DA|0x44;//T3SEL0=1;
899 1 M4_0DA=M4_0DA&0x5F; //T3SEL1=0,R3SEL=0; Single Undirectional Ring Mode
900 1
901 1 M4_04C=0x00;//RTUN1
902 1 M4_04D=0x00;//TTUN1
903 1 M4_04A=M4_04A&0xFD; //RnEN=0
904 1 M4_07C=0x00;//RTUN2
905 1 M4_07D=0x00;//TTUN2
906 1 M4_07A=M4_07A&0xFD; //RnEN=0
907 1 M4_0AC=0x00;
908 1 M4_0AD=0x00;
909 1 M4_0AA=M4_0AA&0xFD; //RnEN=0
910 1 M4_0DC=0x00;
911 1 M4_0DD=0x00;
912 1 M4_0DA=M4_0DA&0xFD; //RnEN=0
913 1
914 1 }
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 3124 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
C51 COMPILER V7.02b LOADM_C 01/18/2005 21:37:57 PAGE 16
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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