at91sam7sxxx.h

at91的一个bootloader

#define UDP_CSR_ENABLE_EP                       (1<<15)
#define UDP_CSR_BYTES_RECEIVED(x)               (((x) >> 16) & 0x7ff)

#define UDP_TRANSCEIVER_CTRL_DISABLE            (1<<8)


//-------------
// Power Management Controller

#define PMC_BASE    (0xfffffc00)

#define PMC_SYS_CLK_ENABLE              REG(PMC_BASE+0x0000)
#define PMC_SYS_CLK_DISABLE             REG(PMC_BASE+0x0004)
#define PMC_SYS_CLK_STATUS              REG(PMC_BASE+0x0008)
#define PMC_PERIPHERAL_CLK_ENABLE       REG(PMC_BASE+0x0010)
#define PMC_PERIPHERAL_CLK_DISABLE      REG(PMC_BASE+0x0014)
#define PMC_PERIPHERAL_CLK_STATUS       REG(PMC_BASE+0x0018)
#define PMC_MAIN_OSCILLATOR             REG(PMC_BASE+0x0020)
#define PMC_MAIN_CLK_FREQUENCY          REG(PMC_BASE+0x0024)
#define PMC_PLL                         REG(PMC_BASE+0x002c)
#define PMC_MASTER_CLK                  REG(PMC_BASE+0x0030)
#define PMC_PROGRAMMABLE_CLK_0          REG(PMC_BASE+0x0040)
#define PMC_PROGRAMMABLE_CLK_1          REG(PMC_BASE+0x0044)
#define PMC_INTERRUPT_ENABLE            REG(PMC_BASE+0x0060)
#define PMC_INTERRUPT_DISABLE           REG(PMC_BASE+0x0064)
#define PMC_INTERRUPT_STATUS            REG(PMC_BASE+0x0068)
#define PMC_INTERRUPT_MASK              REG(PMC_BASE+0x006c)

#define PMC_SYS_CLK_PROCESSOR_CLK               (1<<0)
#define PMC_SYS_CLK_UDP_CLK                     (1<<7)
#define PMC_SYS_CLK_PROGRAMMABLE_CLK_0          (1<<8)
#define PMC_SYS_CLK_PROGRAMMABLE_CLK_1          (1<<9)
#define PMC_SYS_CLK_PROGRAMMABLE_CLK_2          (1<<10)

#define PMC_MAIN_OSCILLATOR_ENABLE              (1<<0)
#define PMC_MAIN_OSCILLATOR_BYPASS              (1<<1)
#define PMC_MAIN_OSCILLATOR_STARTUP_DELAY(x)    ((x)<<8)

#define PMC_PLL_DIVISOR(x)                      (x)
#define PMC_PLL_COUNT_BEFORE_LOCK(x)            ((x)<<8)
#define PMC_PLL_FREQUENCY_RANGE(x)              ((x)<<14)
#define PMC_PLL_MULTIPLIER(x)                   (((x)-1)<<16)
#define PMC_PLL_USB_DIVISOR(x)                  ((x)<<28)

#define PMC_CLK_SELECTION_PLL_CLOCK             (3<<0)
#define PMC_CLK_SELECTION_MAIN_CLOCK            (1<<0)
#define PMC_CLK_SELECTION_SLOW_CLOCK            (0<<0)
#define PMC_CLK_PRESCALE_DIV_1                  (0<<2)
#define PMC_CLK_PRESCALE_DIV_2                  (1<<2)
#define PMC_CLK_PRESCALE_DIV_4                  (2<<2)
#define PMC_CLK_PRESCALE_DIV_8                  (3<<2)
#define PMC_CLK_PRESCALE_DIV_16                 (4<<2)
#define PMC_CLK_PRESCALE_DIV_32                 (5<<2)
#define PMC_CLK_PRESCALE_DIV_64                 (6<<2)


//-------------
// Serial Peripheral Interface (SPI)

#define SPI_BASE    (0xfffe0000)

#define SPI_CONTROL                     REG(SPI_BASE+0x00)
#define SPI_MODE                        REG(SPI_BASE+0x04)
#define SPI_RX_DATA                     REG(SPI_BASE+0x08)
#define SPI_TX_DATA                     REG(SPI_BASE+0x0c)
#define SPI_STATUS                      REG(SPI_BASE+0x10)
#define SPI_INTERRUPT_ENABLE            REG(SPI_BASE+0x14)
#define SPI_INTERRUPT_DISABLE           REG(SPI_BASE+0x18)
#define SPI_INTERRUPT_MASK              REG(SPI_BASE+0x1c)
#define SPI_FOR_CHIPSEL_0               REG(SPI_BASE+0x30)
#define SPI_FOR_CHIPSEL_1               REG(SPI_BASE+0x34)
#define SPI_FOR_CHIPSEL_2               REG(SPI_BASE+0x38)
#define SPI_FOR_CHIPSEL_3               REG(SPI_BASE+0x3c)

#define SPI_CONTROL_ENABLE                  (1<<0)
#define SPI_CONTROL_DISABLE                 (1<<1)
#define SPI_CONTROL_RESET                   (1<<7)
#define SPI_CONTROL_LAST_TRANSFER           (1<<24)

#define SPI_MODE_MASTER                     (1<<0)
#define SPI_MODE_VARIABLE_CHIPSEL           (1<<1)
#define SPI_MODE_CHIPSELS_DECODED           (1<<2)
#define SPI_MODE_USE_DIVIDED_CLOCK          (1<<3)
#define SPI_MODE_MODE_FAULT_DETECTION_OFF   (1<<4)
#define SPI_MODE_LOOPBACK                   (1<<7)
#define SPI_MODE_CHIPSEL(x)                 ((x)<<16)
#define SPI_MODE_DELAY_BETWEEN_CHIPSELS(x)  ((x)<<24)

#define SPI_RX_DATA_CHIPSEL(x)              (((x)>>16)&0xf)

#define SPI_TX_DATA_CHIPSEL(x)              ((x)<<16)
#define SPI_TX_DATA_LAST_TRANSFER           (1<<24)

#define SPI_STATUS_RECEIVE_FULL             (1<<0)
#define SPI_STATUS_TRANSMIT_EMPTY           (1<<1)
#define SPI_STATUS_MODE_FAULT               (1<<2)
#define SPI_STATUS_OVERRUN                  (1<<3)
#define SPI_STATUS_END_OF_RX_BUFFER         (1<<4)
#define SPI_STATUS_END_OF_TX_BUFFER         (1<<5)
#define SPI_STATUS_RX_BUFFER_FULL           (1<<6)
#define SPI_STATUS_TX_BUFFER_EMPTY          (1<<7)
#define SPI_STATUS_NSS_RISING_DETECTED      (1<<8)
#define SPI_STATUS_TX_EMPTY                 (1<<9)
#define SPI_STATUS_SPI_ENABLED              (1<<16)

#define SPI_FOR_CHIPSEL_INACTIVE_CLK_1      (1<<0)
#define SPI_FOR_CHIPSEL_PHASE               (1<<1)
#define SPI_FOR_CHIPSEL_LEAVE_CHIPSEL_LOW   (1<<3)
#define SPI_FOR_CHIPSEL_BITS_IN_WORD(x)     ((x)<<4)
#define SPI_FOR_CHIPSEL_DIVISOR(x)          ((x)<<8)
#define SPI_FOR_CHIPSEL_DELAY_BEFORE_CLK(x) ((x)<<16)
#define SPI_FOR_CHIPSEL_INTERWORD_DELAY(x)  ((x)<<24)

//-------------
// Analog to Digital Converter

#define ADC_BASE        (0xfffd8000)

#define ADC_CONTROL                         REG(ADC_BASE+0x00)
#define ADC_MODE                            REG(ADC_BASE+0x04)
#define ADC_CHANNEL_ENABLE                  REG(ADC_BASE+0x10)
#define ADC_CHANNEL_DISABLE                 REG(ADC_BASE+0x14)
#define ADC_CHANNEL_STATUS                  REG(ADC_BASE+0x18)
#define ADC_STATUS                          REG(ADC_BASE+0x1c)
#define ADC_LAST_CONVERTED_DATA             REG(ADC_BASE+0x20)
#define ADC_INTERRUPT_ENABLE                REG(ADC_BASE+0x24)
#define ADC_INTERRUPT_DISABLE               REG(ADC_BASE+0x28)
#define ADC_INTERRUPT_MASK                  REG(ADC_BASE+0x2c)
#define ADC_CHANNEL_DATA(x)                 REG(ADC_BASE+0x30+(4*(x)))

#define ADC_CONTROL_RESET                       (1<<0)
#define ADC_CONTROL_START                       (1<<1)

#define ADC_MODE_HW_TRIGGERS_ENABLED            (1<<0)
#define ADC_MODE_8_BIT_RESOLUTION               (1<<4)
#define ADC_MODE_SLEEP                          (1<<5)
#define ADC_MODE_PRESCALE(x)                    ((x)<<8)
#define ADC_MODE_STARTUP_TIME(x)                ((x)<<16)
#define ADC_MODE_SAMPLE_HOLD_TIME(x)            ((x)<<24)

#define ADC_CHANNEL(x)                          (1<<(x))

#define ADC_END_OF_CONVERSION(x)                (1<<(x))
#define ADC_OVERRUN_ERROR(x)                    (1<<(8+(x)))
#define ADC_DATA_READY                          (1<<16)
#define ADC_GENERAL_OVERRUN                     (1<<17)
#define ADC_END_OF_RX_BUFFER                    (1<<18)
#define ADC_RX_BUFFER_FULL                      (1<<19)

//-------------
// Synchronous Serial Controller

#define SSC_BASE        (0xfffd4000)

#define SSC_CONTROL                         REG(SSC_BASE+0x00)
#define SSC_CLOCK_DIVISOR                   REG(SSC_BASE+0x04)
#define SSC_RECEIVE_CLOCK_MODE              REG(SSC_BASE+0x10)
#define SSC_RECEIVE_FRAME_MODE              REG(SSC_BASE+0x14)
#define SSC_TRANSMIT_CLOCK_MODE             REG(SSC_BASE+0x18)
#define SSC_TRANSMIT_FRAME_MODE             REG(SSC_BASE+0x1c)
#define SSC_RECEIVE_HOLDING                 REG(SSC_BASE+0x20)
#define SSC_TRANSMIT_HOLDING                REG(SSC_BASE+0x24)
#define SSC_RECEIVE_SYNC_HOLDING            REG(SSC_BASE+0x30)
#define SSC_TRANSMIT_SYNC_HOLDING           REG(SSC_BASE+0x34)
#define SSC_STATUS                          REG(SSC_BASE+0x40)
#define SSC_INTERRUPT_ENABLE                REG(SSC_BASE+0x44)
#define SSC_INTERRUPT_DISABLE               REG(SSC_BASE+0x48)
#define SSC_INTERRUPT_MASK                  REG(SSC_BASE+0x4c)

#define SSC_CONTROL_RX_ENABLE                   (1<<0)
#define SSC_CONTROL_RX_DISABLE                  (1<<1)
#define SSC_CONTROL_TX_ENABLE                   (1<<8)
#define SSC_CONTROL_TX_DISABLE                  (1<<9)
#define SSC_CONTROL_RESET                       (1<<15)

#define SSC_CLOCK_MODE_SELECT(x)                ((x)<<0)
#define SSC_CLOCK_MODE_OUTPUT(x)                ((x)<<2)
#define SSC_CLOCK_MODE_INVERT                   (1<<5)
#define SSC_CLOCK_MODE_START(x)                 ((x)<<8)
#define SSC_CLOCK_MODE_START_DELAY(x)           ((x)<<16)
#define SSC_CLOCK_MODE_FRAME_PERIOD(x)          ((x)<<24)

#define SSC_FRAME_MODE_BITS_IN_WORD(x)          (((x)-1)<<0)
#define SSC_FRAME_MODE_LOOPBACK                 (1<<5) // for RX
#define SSC_FRAME_MODE_DEFAULT_IS_1             (1<<5) // for TX
#define SSC_FRAME_MODE_MSB_FIRST                (1<<7)
#define SSC_FRAME_MODE_WORDS_PER_TRANSFER(x)    ((x)<<8)
#define SSC_FRAME_MODE_FRAME_SYNC_LEN(x)        ((x)<<16)
#define SSC_FRAME_MODE_FRAME_SYNC_TYPE(x)       ((x)<<20)
#define SSC_FRAME_MODE_SYNC_DATA_ENABLE         (1<<23) // for TX only
#define SSC_FRAME_MODE_NEGATIVE_EDGE            (1<<24)

#define SSC_STATUS_TX_READY                     (1<<0)
#define SSC_STATUS_TX_EMPTY                     (1<<1)
#define SSC_STATUS_TX_ENDED                     (1<<2)
#define SSC_STATUS_TX_BUF_EMPTY                 (1<<3)
#define SSC_STATUS_RX_READY                     (1<<4)
#define SSC_STATUS_RX_OVERRUN                   (1<<5)
#define SSC_STATUS_RX_ENDED                     (1<<6)
#define SSC_STATUS_RX_BUF_FULL                  (1<<7)
#define SSC_STATUS_TX_SYNC_OCCURRED             (1<<10)
#define SSC_STATUS_RX_SYNC_OCCURRED             (1<<11)
#define SSC_STATUS_TX_ENABLED                   (1<<16)
#define SSC_STATUS_RX_ENABLED                   (1<<17)


//-------------
// Peripheral DMA Controller
//
// There is one set of registers for every peripheral that supports DMA.

#define PDC_RX_POINTER(x)                   REG((x)+0x100)
#define PDC_RX_COUNTER(x)                   REG((x)+0x104)
#define PDC_TX_POINTER(x)                   REG((x)+0x108)
#define PDC_TX_COUNTER(x)                   REG((x)+0x10c)
#define PDC_RX_NEXT_POINTER(x)              REG((x)+0x110)
#define PDC_RX_NEXT_COUNTER(x)              REG((x)+0x114)
#define PDC_TX_NEXT_POINTER(x)              REG((x)+0x118)
#define PDC_TX_NEXT_COUNTER(x)              REG((x)+0x11c)
#define PDC_CONTROL(x)                      REG((x)+0x120)
#define PDC_STATUS(x)                       REG((x)+0x124)

#define PDC_RX_ENABLE                       REG(1<<0)
#define PDC_RX_DISABLE                      REG(1<<1)
#define PDC_TX_ENABLE                       REG(1<<8)
#define PDC_TX_DISABLE                      REG(1<<9)


#endif