📄 at91sam7sxxx.h
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//-----------------------------------------------------------------------------
// Incomplete register definitions for the AT91SAM7Sxxx chip.
// Jonathan Westhues, Jul 2005
//-----------------------------------------------------------------------------
#ifndef __AT91SAM7S128_H
#define __AT91SAM7S128_H
typedef unsigned char BYTE;
typedef signed char SBYTE;
typedef unsigned short WORD;
typedef signed short SWORD;
typedef unsigned long DWORD;
typedef signed long SDWORD;
typedef int BOOL;
#define TRUE 1
#define FALSE 0
#define REG(x) (*(volatile DWORD *)(x))
//-------------
// Peripheral IDs
#define PERIPH_AIC_FIQ 0
#define PERIPH_SYSIRQ 1
#define PERIPH_PIOA 2
#define PERIPH_ADC 4
#define PERIPH_SPI 5
#define PERIPH_US0 6
#define PERIPH_US1 7
#define PERIPH_SSC 8
#define PERIPH_TWI 9
#define PERIPH_PWMC 10
#define PERIPH_UDP 11
#define PERIPH_TC0 12
#define PERIPH_TC1 13
#define PERIPH_TC2 14
#define PERIPH_AIC_IRQ0 30
#define PERIPH_AIC_IRQ1 31
//-------------
// Reset Controller
#define RSTC_BASE (0xfffffd00)
#define RSTC_CONTROL REG(RSTC_BASE+0x00)
#define RST_CONTROL_KEY (0xa5<<24)
#define RST_CONTROL_PROCESSOR_RESET (1<<0)
//-------------
// PWM Controller
#define PWM_BASE (0xfffcc000)
#define PWM_MODE REG(PWM_BASE+0x00)
#define PWM_ENABLE REG(PWM_BASE+0x04)
#define PWM_DISABLE REG(PWM_BASE+0x08)
#define PWM_STATUS REG(PWM_BASE+0x0c)
#define PWM_INTERRUPT_ENABLE REG(PWM_BASE+0x10)
#define PWM_INTERRUPT_DISABLE REG(PWM_BASE+0x14)
#define PWM_INTERRUPT_MASK REG(PWM_BASE+0x18)
#define PWM_INTERRUPT_STATUS REG(PWM_BASE+0x1c)
#define PWM_CH_MODE(x) REG(PWM_BASE+0x200+((x)*0x20))
#define PWM_CH_DUTY_CYCLE(x) REG(PWM_BASE+0x204+((x)*0x20))
#define PWM_CH_PERIOD(x) REG(PWM_BASE+0x208+((x)*0x20))
#define PWM_CH_COUNTER(x) REG(PWM_BASE+0x20c+((x)*0x20))
#define PWM_CH_UPDATE(x) REG(PWM_BASE+0x210+((x)*0x20))
#define PWM_MODE_DIVA(x) ((x)<<0)
#define PWM_MODE_PREA(x) ((x)<<8)
#define PWM_MODE_DIVB(x) ((x)<<16)
#define PWM_MODE_PREB(x) ((x)<<24)
#define PWM_CHANNEL(x) (1<<(x))
#define PWM_CH_MODE_PRESCALER(x) ((x)<<0)
#define PWM_CH_MODE_PERIOD_CENTER_ALIGNED (1<<8)
#define PWM_CH_MODE_POLARITY_STARTS_HIGH (1<<9)
#define PWM_CH_MODE_UPDATE_UPDATES_PERIOD (1<<10)
//-------------
// Embedded Flash Controller
#define MC_BASE (0xffffff00)
#define MC_FLASH_MODE REG(MC_BASE+0x60)
#define MC_FLASH_COMMAND REG(MC_BASE+0x64)
#define MC_FLASH_STATUS REG(MC_BASE+0x68)
#define MC_FLASH_MODE_READY_INTERRUPT_ENABLE (1<<0)
#define MC_FLASH_MODE_LOCK_INTERRUPT_ENABLE (1<<2)
#define MC_FLASH_MODE_PROG_ERROR_INTERRUPT_ENABLE (1<<3)
#define MC_FLASH_MODE_NO_ERASE_BEFORE_PROGRAMMING (1<<7)
#define MC_FLASH_MODE_FLASH_WAIT_STATES(x) ((x)<<8)
#define MC_FLASH_MODE_MASTER_CLK_IN_MHZ(x) ((x)<<16)
#define MC_FLASH_COMMAND_FCMD(x) ((x)<<0)
#define MC_FLASH_COMMAND_PAGEN(x) ((x)<<8)
#define MC_FLASH_COMMAND_KEY ((0x5a)<<24)
#define FCMD_NOP 0x0
#define FCMD_WRITE_PAGE 0x1
#define FCMD_SET_LOCK_BIT 0x2
#define FCMD_WRITE_PAGE_LOCK 0x3
#define FCMD_CLEAR_LOCK_BIT 0x4
#define FCMD_ERASE_ALL 0x8
#define FCMD_SET_GP_NVM_BIT 0xb
#define FCMD_SET_SECURITY_BIT 0xf
#define MC_FLASH_STATUS_READY (1<<0)
#define MC_FLASH_STATUS_LOCK_ERROR (1<<2)
#define MC_FLASH_STATUS_PROGRAMMING_ERROR (1<<3)
#define MC_FLASH_STATUS_SECURITY_BIT_ACTIVE (1<<4)
#define MC_FLASH_STATUS_GP_NVM_ACTIVE_0 (1<<8)
#define MC_FLASH_STATUS_GP_NVM_ACTIVE_1 (1<<9)
#define MC_FLASH_STATUS_LOCK_ACTIVE(x) (1<<((x)+16))
#define FLASH_PAGE_SIZE_BYTES 256
#define FLASH_PAGE_COUNT 512
//-------------
// Watchdog Timer
#define WDT_BASE (0xfffffd40)
#define WDT_CONTROL REG(WDT_BASE+0x00)
#define WDT_MODE REG(WDT_BASE+0x04)
#define WDT_STATUS REG(WDT_BASE+0x08)
#define WDT_HIT() WDT_CONTROL = 0xa5000001
#define WDT_MODE_COUNT(x) ((x)<<0)
#define WDT_MODE_INTERRUPT_ON_EVENT (1<<12)
#define WDT_MODE_RESET_ON_EVENT_ENABLE (1<<13)
#define WDT_MODE_RESET_ON_EVENT (1<<14)
#define WDT_MODE_WATCHDOG_DELTA(x) ((x)<<16)
#define WDT_MODE_HALT_IN_DEBUG_MODE (1<<28)
#define WDT_MODE_HALT_IN_IDLE_MODE (1<<29)
#define WDT_MODE_DISABLE (1<<15)
//-------------
// Parallel Input/Output Controller
#define PIO_BASE (0xfffff400)
#define PIO_ENABLE REG(PIO_BASE+0x000)
#define PIO_DISABLE REG(PIO_BASE+0x004)
#define PIO_STATUS REG(PIO_BASE+0x008)
#define PIO_OUTPUT_ENABLE REG(PIO_BASE+0x010)
#define PIO_OUTPUT_DISABLE REG(PIO_BASE+0x014)
#define PIO_OUTPUT_STATUS REG(PIO_BASE+0x018)
#define PIO_GLITCH_ENABLE REG(PIO_BASE+0x020)
#define PIO_GLITCH_DISABLE REG(PIO_BASE+0x024)
#define PIO_GLITCH_STATUS REG(PIO_BASE+0x028)
#define PIO_OUTPUT_DATA_SET REG(PIO_BASE+0x030)
#define PIO_OUTPUT_DATA_CLEAR REG(PIO_BASE+0x034)
#define PIO_OUTPUT_DATA_STATUS REG(PIO_BASE+0x038)
#define PIO_PIN_DATA_STATUS REG(PIO_BASE+0x03c)
#define PIO_OPEN_DRAIN_ENABLE REG(PIO_BASE+0x050)
#define PIO_OPEN_DRAIN_DISABLE REG(PIO_BASE+0x054)
#define PIO_OPEN_DRAIN_STATUS REG(PIO_BASE+0x058)
#define PIO_NO_PULL_UP_ENABLE REG(PIO_BASE+0x060)
#define PIO_NO_PULL_UP_DISABLE REG(PIO_BASE+0x064)
#define PIO_NO_PULL_UP_STATUS REG(PIO_BASE+0x068)
#define PIO_PERIPHERAL_A_SEL REG(PIO_BASE+0x070)
#define PIO_PERIPHERAL_B_SEL REG(PIO_BASE+0x074)
#define PIO_PERIPHERAL_WHICH REG(PIO_BASE+0x078)
#define PIO_OUT_WRITE_ENABLE REG(PIO_BASE+0x0a0)
#define PIO_OUT_WRITE_DISABLE REG(PIO_BASE+0x0a4)
#define PIO_OUT_WRITE_STATUS REG(PIO_BASE+0x0a8)
//-------------
// USB Device Port
#define UDP_BASE (0xfffb0000)
#define UDP_FRAME_NUMBER REG(UDP_BASE+0x0000)
#define UDP_GLOBAL_STATE REG(UDP_BASE+0x0004)
#define UDP_FUNCTION_ADDR REG(UDP_BASE+0x0008)
#define UDP_INTERRUPT_ENABLE REG(UDP_BASE+0x0010)
#define UDP_INTERRUPT_DISABLE REG(UDP_BASE+0x0014)
#define UDP_INTERRUPT_MASK REG(UDP_BASE+0x0018)
#define UDP_INTERRUPT_STATUS REG(UDP_BASE+0x001c)
#define UDP_INTERRUPT_CLEAR REG(UDP_BASE+0x0020)
#define UDP_RESET_ENDPOINT REG(UDP_BASE+0x0028)
#define UDP_ENDPOINT_CSR(x) REG(UDP_BASE+0x0030+((x)*4))
#define UDP_ENDPOINT_FIFO(x) REG(UDP_BASE+0x0050+((x)*4))
#define UDP_TRANSCEIVER_CTRL REG(UDP_BASE+0x0074)
#define UDP_GLOBAL_STATE_ADDRESSED (1<<0)
#define UDP_GLOBAL_STATE_CONFIGURED (1<<1)
#define UDP_GLOBAL_STATE_SEND_RESUME_ENABLED (1<<2)
#define UDP_GLOBAL_STATE_RESUME_RECEIVED (1<<3)
#define UDP_GLOBAL_STATE_REMOTE_WAKE_UP_ENABLED (1<<4)
#define UDP_FUNCTION_ADDR_ENABLED (1<<8)
#define UDP_INTERRUPT_ENDPOINT(x) (1<<(x))
#define UDP_INTERRUPT_SUSPEND (1<<8)
#define UDP_INTERRUPT_RESUME (1<<9)
#define UDP_INTERRUPT_EXTERNAL_RESUME (1<<10)
#define UDP_INTERRUPT_SOF (1<<11)
#define UDP_INTERRUPT_END_OF_BUS_RESET (1<<12)
#define UDP_INTERRUPT_WAKEUP (1<<13)
#define UDP_RESET_ENDPOINT_NUMBER(x) (1<<(x))
#define UDP_CSR_TX_PACKET_ACKED (1<<0)
#define UDP_CSR_RX_PACKET_RECEIVED_BANK_0 (1<<1)
#define UDP_CSR_RX_HAVE_READ_SETUP_DATA (1<<2)
#define UDP_CSR_STALL_SENT (1<<3)
#define UDP_CSR_TX_PACKET (1<<4)
#define UDP_CSR_FORCE_STALL (1<<5)
#define UDP_CSR_RX_PACKET_RECEIVED_BANK_1 (1<<6)
#define UDP_CSR_CONTROL_DATA_DIR (1<<7)
#define UDP_CSR_EPTYPE_CONTROL (0<<8)
#define UDP_CSR_EPTYPE_ISOCHRON_OUT (1<<8)
#define UDP_CSR_EPTYPE_ISOCHRON_IN (5<<8)
#define UDP_CSR_EPTYPE_BULK_OUT (2<<8)
#define UDP_CSR_EPTYPE_BULK_IN (6<<8)
#define UDP_CSR_EPTYPE_INTERRUPT_OUT (3<<8)
#define UDP_CSR_EPTYPE_INTERRUPT_IN (7<<8)
#define UDP_CSR_IS_DATA1 (1<<11)
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