mean_64.vhd

原创代码

library  ieee;
use  ieee.std_logic_1164.all;
USE  IEEE.STD_LOGIC_UNSIGNED.ALL;
use  IEEE.std_logic_arith.all;

entity Mean_64 is
port (clk,reset,en: in std_logic; 
      AD_in: in std_logic_vector(10 downto 1);       ------数字采样信号输入---
      Ave_out: out std_logic_vector(10 downto 1)     --------平均值输出------  
      );
end Mean_64;

architecture action of Mean_64 is

----------------------------------------------------------------------------
signal count: std_logic_vector(7 downto 1);--------上电计数器，快速均值控制-----------

signal data1,data2,data3,data4,data5:  std_logic_vector(64 downto 1);-----暂存器-------
signal data6,data7,data8,data9,data10:  std_logic_vector(64 downto 1);

signal mov_reg_out:  std_logic_vector(10 downto 1);----第64个数据输出寄存器----
signal add_reg:  std_logic_vector(16 downto 1);------累加器------

signal sub_reg:   std_logic_vector(10 downto 1);---------第1个数据与第65个数据求差----
signal sub_stat:   std_logic; ----------第1个数据与第65个数据比较状态指示----

signal average_xn: std_logic_vector(10 downto 1);------均值输出寄存器--------------
--------------------------------------------------------------------------------------------
begin

Ave_out<=average_xn;------------均值输出--------
mov_reg_out<=data10(64) & data9(64) & data8(64) & data7(64) & data6(64) & data5(64) & data4(64) & data3(64) & data2(64) & data1(64) ;
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-----------------------上电与复位计数，识别初始化过程，66 个 clk ---------------------------------------------------
count_set:  process(clk,count,reset,en) 
            begin
            if reset='1' then
               count<="0000000";
            else
             if en='1' then
                if clk'event and clk='1' then
                  if count < "1000001" then
                   count<=count+1;
                   end if;
                 end if;
               end if;
              end if;
            end process count_set;   
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-------------------------以下求AD输入xn的64点均值--------------------------------------------------------------

aa: process(clk,AD_in,reset,en) ---- mov reg 移位寄存64组AD输入
    begin

    if reset='1' then
       data1<="0000000000000000000000000000000000000000000000000000000000000000";
       data2<="0000000000000000000000000000000000000000000000000000000000000000";
       data3<="0000000000000000000000000000000000000000000000000000000000000000";
       data4<="0000000000000000000000000000000000000000000000000000000000000000";
       data5<="0000000000000000000000000000000000000000000000000000000000000000";
       data6<="0000000000000000000000000000000000000000000000000000000000000000";
       data7<="0000000000000000000000000000000000000000000000000000000000000000";
       data8<="0000000000000000000000000000000000000000000000000000000000000000";
       data9<="0000000000000000000000000000000000000000000000000000000000000000";
      data10<="0000000000000000000000000000000000000000000000000000000000000000";
     else
        if en='1' then
        if clk'event and clk='1' then
        
       dmov_reg:  for i in 64 downto 2 loop
                 data1(i)<=data1(i-1);
                 data2(i)<=data2(i-1);
                 data3(i)<=data3(i-1);
                 data4(i)<=data4(i-1);
                 data5(i)<=data5(i-1);
                 data6(i)<=data6(i-1);
                 data7(i)<=data7(i-1);
                 data8(i)<=data8(i-1);
                 data9(i)<=data9(i-1);
                 data10(i)<=data10(i-1);
                end loop dmov_reg;
                 data1(1) <=AD_in(1);
                 data2(1) <=AD_in(2);
                 data3(1) <=AD_in(3);
                 data4(1) <=AD_in(4);
                 data5(1) <=AD_in(5);
                 data6(1) <=AD_in(6);
                 data7(1) <=AD_in(7);
                 data8(1) <=AD_in(8);
                 data9(1) <=AD_in(9);
                 data10(1) <=AD_in(10);
       end if;
      end if;
   end if;
  end process aa;

bb: process(clk,reset,en,AD_in,mov_reg_out)  --- 求xn均值时累加器输入求差运算，
    begin                                      ----若AD输入大于寄存器第64个值做AD_in - data_reg_out运算状态置1
    if reset='1' then
      sub_reg<="0000000000";
    else 
    if en='1' then
     if clk'event and clk='1' then
          if AD_in > mov_reg_out then
            sub_reg<=AD_in - mov_reg_out;
            sub_stat<='1';
          else
            sub_reg<= mov_reg_out - AD_in;
             sub_stat<='0';
         end if;
       end if;
      end if;
     end if;
  end process bb;

CC:process(clk,sub_stat,sub_reg,reset,en)  ----64点求和计算-----
   begin
    if reset='1' then
    add_reg<="0000000000000000";
    else  
     if en='1' then   
      if clk'event and clk='1' then          
            if sub_stat='1' then
            add_reg <= add_reg + sub_reg;
            else 
            add_reg<=add_reg - sub_reg;
            end if;
         end if;
      end if;
     end if;
    end process cc;

average_out: process(add_reg,clk,en,reset,count)----------- xn 均值输出，减少均值输出等待时间，3个clk 即可输出均值---------
             begin 
             if reset='1' then
               average_xn<="0000000000";
             else
                if en='1' then
                 if  clk='1' and clk'event then
                  case count is
                  when "0000010" =>  average_xn <= add_reg(10 downto 1);  ----------- 均值为累加器10-1位-------   
                  when "0000101" =>  average_xn <= add_reg(12 downto 3);  ----------- 均值为累加器12-3位-------   
                  when "0001001" =>  average_xn <= add_reg(13 downto 4);  ----------- 均值为累加器13-4位-------  
                  when "0010001" =>  average_xn <= add_reg(14 downto 5);  ----------- 均值为累加器14-5位-------   
                  when "0100001" =>  average_xn <= add_reg(15 downto 6);  ----------- 均值为累加器16-6位-------   
                  when "1000001" =>  average_xn <= add_reg(16 downto 7);  ----------- 均值为累加器17-7位-------   
                  when others =>      null;
                  end case;
                  end if;
                end if;
            end if;
            end process average_out;
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 end action;